1/12July 2001
■ HIGH SPEED :
f
MAX
= 67MHz (TYP.) at V
CC
= 6V
■ LOW POWER DISSIPATION:
I
CC
=2µA(MAX.) at T
A
=25°C
■ HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
■ BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL
■ WIDE OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 109
DESCRIPTION
The M74HC109 is an high speed CMOS DUAL
J-K FLIP FLOP WITH PRESET AND CLEAR
fabricated with silicon gate C
2
MOS technology. In
accordance with the logic level on the J and K
input this device changes state on positive going
transition of the clock pulse. CLEAR and PRESET
are independent of the clock and are
accomplished by a logic low on the corresponding
input.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC109
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE TUBE T & R
DIP M74HC109B1R
SOP M74HC109M1R M74HC109RM13TR
TSSOP M74HC109TTR
TSSOPDIP SOP
