M28W320CT90N6 Datasheet M28W320CT90N6 | P13-P15

13/53

M28W320CT, M28W320CB

memory location must be erased and repro-

grammed.

See Appendix C, Figure 21, Program Flowchart

and Pseudo Code, for the flowchart for using the

Program command.

Double Word Program Command

This feature is offered to improve the programming

throughput, writing a page of two adjacent words

in parallel.The two words must differ only for the

address A0. Programming should not be attempt-

ed when V

is not at V

PPH

. The command can be

executed if V

is below V

PPH

but the result is not

guaranteed.

Three bus write cycles are necessary to issue the

Double Word Program command.

■ The first bus cycle sets up the Double Word

Program Command.

■ The second bus cycle latches the Address and

theDataofthefirstwordtobewritten.

■ The third bus cycle latches the Address and the

Data of the second word to be written and starts

the Program/Erase Controller.

Read operations output the Status Register con-

tent after the programming has started. Program-

ming aborts if Reset goes to V

. As data integrity

cannot be guaranteed when the program opera-

tion is aborted, the block containing the memory

location must be erased and reprogrammed.

See Appendix C, Figure 22, Double Word Pro-

gram Flowchart and Pseudo Code, for the flow-

chart for using the Double Word Program

command.

Clear Status Register Command

The Clear Status Register command can be used

to reset bits 1, 3, 4 and 5 in the Status Register to

‘0’. One bus write cycle is required to issue the

Clear Status Register command.

The bits in the Status Register do not automatical-

ly return to ‘0’ when a new Program or Erase com-

mand is issued. The error bits in the Status

new Program or Erase command.

Program/Erase Suspend Command

The Program/Erase Suspend command is used to

pause a Program or Erase operation. One bus

write cycle is required to issue the Program/Erase

command and pause the Program/Erase control-

ler.

During Program/Erase Suspend the Command In-

terface will accept the Program/Erase Resume,

Read Array, Read Status Register, Read Electron-

ic Signature and Read CFI Query commands. Ad-

ditionally, if the suspend operation was Erase then

the Program, Block Lock, Block Lock-Down or

Protection Program commands will also be ac-

cepted. The block being erased may be protected

by issuing the Block Protect, Block Lock or Protec-

tion Program commands. When the Program/

Erase Resume command is issued the operation

will complete. Only the blocks not being erased

may be read or programmed correctly.

During a Program/Erase Suspend, the device can

be placed in a pseudo-standby mode by taking

Chip Enable to V

. Program/Erase is aborted if

Reset turns to V

See Appendix C, Figure 23, Program or Double

Word Program Suspend & Resume Flowchart and

Pseudo Code, and Figure 25, Erase Suspend &

Resume Flowchart and Pseudo Code for flow-

charts for using the Program/Erase Suspend com-

mand.

Program/Erase Resume Command

The Program/Erase Resume command can be

used to restart the Program/Erase Controller after

a Program/Erase Suspend operation has paused

it. One Bus Write cycle is required to issue the

command. Once the command is issued subse-

quent Bus Read operations read the Status Reg-

ister.

See Appendix C, Figure 23, Program or Double

Word Program Suspend & Resume Flowchart and

Pseudo Code, and Figure 25, Erase Suspend &

Resume Flowchart and Pseudo Code for flow-

charts for using the Program/Erase Resume com-

mand.

Protection Register Program Command

The Protection Register Program command is

used to Program the 64 bit user One-Time-Pro-

grammable (OTP) segment of the Protection Reg-

ister. The segment is programmed 16 bits at a

time. When shipped all bits in the segment are set

to ‘1’. The user can only program the bits to ‘0’.

Two write cycles are required to issue the Protec-

tion Register Program command.

■ The first bus cycle sets up the Protection

■ The second latches the Address and the Data to

be written to the Protection Register and starts

the Program/Erase Controller.

Read operations output the Status Register con-

tent after the programming has started.

The segment can be protected by programming bit

1 of the Protection Lock Register. Bit 1 of the Pro-

tection Lock Register protects bit 2 of the Protec-

tion Lock Register. Programming bit 2 of the

Protection Lock Register will result in a permanent

protection of the Security Block (see Figure 7, Se-

curity Block and Protection Register Memory

Map). Attempting to program a previously protect-

ed Protection Register will result in a Status Reg-

ister error. The protection of the Protection

M28W320CT, M28W320CB

14/53

ible.

The Protection Register Program cannot be sus-

pended.

Block Lock Command

The Block Lock command is used to lock a block

and prevent Program or Erase operations from

changing the data in it. All blocks are locked at

power-up or reset.

Two Bus Write cycles are required to issue the

Block Lock command.

■ The first bus cycle sets up the Block Lock

command.

■ The second Bus Write cycle latches the block

address.

The lock status can be monitored for each block

using the Read Electronic Signature command.

Table. 9 shows the protection status after issuing

a Block Lock command.

The Block Lock bits are volatile, once set they re-

main set until a hardware reset or power-down/

power-up. They are cleared by a Blocks Unlock

command. Refer to the section, Block Locking, for

a detailed explanation.

Block Unlock Command

The Blocks Unlock command is used to unlock a

block, allowing the block to be programmed or

erased. Two Bus Write cycles are required to is-

sue the Blocks Unlock command.

■ The first bus cycle sets up the Block Unlock

command.

■ The second Bus Write cycle latches the block

address.

The lock status can be monitored for each block

using the Read Electronic Signature command.

Table. 9 shows the protection status after issuing

a Block Unlock command. Refer to the section,

Block Locking, for a detailed explanation.

Block Lock-Down Command

A locked block cannot be Programmed or Erased,

or have its protection status changed when WP

low, V

.WhenWPis high, V

IH,

the Lock-Down

function is disabled and the locked blocks can be

individually unlocked by the Block Unlock com-

mand.

Two Bus Write cycles are required to issue the

Block Lock-Down command.

■ The first bus cycle sets up the Block Lock

command.

■ The second Bus Write cycle latches the block

address.

The lock status can be monitored for each block

using the Read Electronic Signature command.

Locked-Down blocks revert to the locked (and not

locked-down) state when the device is reset on

power-down. Table. 9 shows the protection status

after issuing a Block Lock-Down command. Refer

to the section, Block Locking, for a detailed expla-

nation.

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M28W320CT, M28W320CB

Table 3. Commands

Note: 1. X = Don't Care.

2. The signature addresses are listed in Tables 4, 5 and 6.

3. Addr 1 and Addr 2 must be consecutive Addresses differing only for A0.

Table 4. Read Electronic Signature

Note: RP =V

Commands

No. of

Cycles

Bus Write Operations

1st Cycle 2nd Cycle 3nd Cycle

Bus

Op.

Addr Data

Bus

Op.

Addr Data

Bus

Op.

Addr Data

Read Memory Array 1+ Write X FFh

Read

Addr

Data

Read Status Register 1+ Write X 70h

Read

Status

Read Electronic Signature 1+ Write X 90h

Read

Signature

Addr

(2)

Signature

Read CFI Query 1+ Write X 98h Read CFI Addr Query

Erase 2 Write X 20h Write

Block

Addr

D0h

Program 2 Write X

40h or

10h

Write Addr

Data

Input

Double Word Program

(3)

3 Write X 30h Write Addr 1

Data

Input

Write Addr 2

Data

Input

Clear Status Register 1 Write X 50h

Program/Erase Suspend 1 Write X B0h

Program/Erase Resume 1 Write X D0h

Block Lock 2 Write X 60h Write

Block

Address

01h

Block Unlock 2 Write X 60h Write

Block

Address

D0h

Block Lock-Down 2 Write X 60h Write

Block

Address

2Fh

Protection Register

Program

2 Write X C0h Write

Address

Data

Input

Code Device E G W A0 A1 A2-A7 A8-A20 DQ0-DQ7 DQ8-DQ15

Manufacture.

Code

0 Don't Care 20h 00h

Device Code

M28W320CT

0 Don't Care BAh 88h

M28W320CB

0 Don't Care BBh 88h

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P53

M28W320CT90N6

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Manufacturer:

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Description:

NOR Flash 32M (2Mx16) 90ns

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