12
LTC1923
1923f
PROTECTION FEATURES
Many protection features have been integrated into the
LTC1923 to ensure that the TEC is not overstressed or the
system does not thermally run away. These features
include pulse-by-pulse current limiting, TEC voltage clamp-
ing and open/shorted thermistor detection.
Current Limit
The peak current in the full bridge during each switching
cycle can be limited by placing a sense resistor, R
S
, from
the common NMOS source connections of MNA and MNB
to ground. The CS
+
and CS
–
connections should be made
as shown in Figure 1. Current limit is comprised of a fixed
gain of ten differential amplifier, an attenuator (resistor
divider) and a current limit comparator. A detailed diagram
of the circuitry is shown in Figure 3. The differential
amplifier output, I
TEC
, is provided to allow the user the
ability to monitor the instantaneous current flowing in the
bridge. If an average current is desired, an external RC
filter can be used to filter the I
TEC
output. Approximately
50ns of leading edge blanking is also internally integrated
to prevent nuisance tripping of the current sense circuitry.
It relieves the filtering requirements for the CS input pins.
During a switching cycle, current limit occurs when the
voltage on I
TEC
exceeds the lowest of the following three
conditions: 1) 1.5 times the voltage on the SS pin, 2) 1.5
times the voltage on the I
LIM
pin or 3) 1.5V. When a
current limit condition is sensed, all four external FETs are
immediately shut off. These devices are turned back on
only after C
T
reaches the same state (either charging or
OPERATIO
U
discharging) as when the current limit condition oc-
curred. For instance, if C
T
is charging when current limit
occurs, the outputs are forced off for the remainder of this
charging time, the entire C
T
discharge time, and are only
re-enabled when C
T
reaches its valley voltage and begins
charging again. An analogous sequence of events occurs
if current limit is tripped while C
T
is being discharged.
The full-bridge current can be soft-started (gradually
increased) by placing a capacitor from the SS pin to
ground. A 1.5µA current is sourced from the chip and will
charge the capacitor. This limits the inrush current at start-
up and allows the current delivered to the TEC to be linearly
increased from zero.
The LTC1923 features a dedicated pin, I
LIM
, to adjust
current limit. If the voltage placed on I
LIM
is greater than
1V, the default current limit, I
LIMIT
, is:
I
LIMIT
= 150mV/R
S
where R
S
= the current sense resistor.
Utilizing the I
LIM
pin allows the current limit threshold to
be easily set and adjusted (the current limit threshold can
also be adjusted by changing R
S
). More importantly, it
facilitates independent setting of the heating and cooling
current limits with the addition of one transistor. Figure 4
shows how to implement this using three resistors and an
external NMOS, M1. In many applications, a higher cool-
ing capability is desired. When TEC
+
is greater than
TEC
–
, the H/C output is in a low state signifying that the
system is being cooled (this is typical for most lasers).
–
+
A = 10
R
2R 1V
NDRVB
CURRENT SENSE
AMPLIFIER
PULSE-BY-PULSE
CURRENT LIMIT
TEC
–
CS
+
CS
–
NDRVATEC
+
NDRVB
OSCILLATOR
PEAK/VALLEY
NDRVA
I
TEC
I
LIM
SS
1.5µA
INPUT SELECT
LEB
S
1923 F03
SHUT
OUTPUTS
OFF
R
Q
–
–
–
+
Figure 3. Current Sense Circuitry
