Philips Semiconductors Product specification
8XC54/58
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
2000 Aug 07
33
(8XC51RX+ ONLY)
Expanded Data RAM Addressing
(8XC51RX+ ONLY)
The 8XC51RX+ have internal data memory that is mapped into four
separate segments: the lower 128 bytes of RAM, upper 128 bytes of
RAM, 128 bytes Special Function Register (SFR), and 256 bytes
(768 for RD+) expanded RAM (EXTRAM).
The four segments are:
1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are
directly and indirectly addressable.
2. The Upper 128 bytes of RAM (addresses 80H to FFH) are
indirectly addressable only.
3. The Special Function Registers, SFRs, (addresses 80H to FFH)
are directly addressable only.
4. The 256-bytes (768 for RD+) expanded RAM ((EXTRAM
(256-bytes) 00H–FFH)) and ((EXTRAM (768-bytes for RD+)
00H – 2FFH)) are indirectly accessed by move external instruction,
MOVX, and with the EXTRAM bit cleared, see Figure 27.
The Lower 128 bytes can be accessed by either direct or indirect
addressing. The Upper 128 bytes can be accessed by indirect
addressing only. The Upper 128 bytes occupy the same address
space as the SFR. That means they have the same address, but are
physically separate from SFR space.
When an instruction accesses an internal location above address
7FH, the CPU knows whether the access is to the upper 128 bytes
of data RAM or to SFR space by the addressing mode used in the
instruction. Instructions that use direct addressing access SFR
space. For example:
MOV 0A0H,#data
accesses the SFR at location 0A0H (which is P2). Instructions that
use indirect addressing access the Upper 128 bytes of data RAM.
For example:
MOV @R0,#data
where R0 contains 0A0H, accesses the data byte at address 0A0H,
rather than P2 (whose address is 0A0H).
The EXTRAM can be accessed by indirect addressing, with
EXTRAM bit cleared and MOVX instructions. This part of memory is
physically located on-chip, logically occupies the first 256-bytes (768
for RD+) of external data memory.
With EXTRAM = 0, the EXTRAM is indirectly addressed, using the
MOVX instruction in combination with any of the registers R0, R1 of
the selected bank or DPTR. An access to EXTRAM will not affect
ports P0, P3.6 (WR#) and P3.7 (RD#). P2 SFR is output during
external addressing. For example, with EXTRAM = 0,
MOVX @R0,#data
where R0 contains 0A0H, access the EXTRAM at address 0A0H
rather than external memory. An access to external data memory
locations higher than FFH (2FF for RD+) (i.e., 0100H to FFFFH) will
be performed with the MOVX DPTR instructions in the same way as
in the standard 80C51, so with P0 and P2 as data/address bus, and
P3.6 and P3.7 as write and read timing signals. Refer to Figure 28.
With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar
to the standard 80C51. MOVX @ Ri will provide an 8-bit address
multiplexed with data on Port 0 and any output port pins can be
used to output higher order address bits. This is to provide the
external paging capability. MOVX @DPTR will generate a 16-bit
address. Port 2 outputs the high-order eight address bits (the
contents of DPH) while Port 0 multiplexes the low-order eight
address bits (DPL) with data. MOVX @Ri and MOVX @DPTR will
generate either read or write signals on P3.6 (#WR) and P3.7 (#RD).
The stack pointer (SP) may be located anywhere in the 256 bytes
RAM (lower and upper RAM) internal data memory. The stack may
not be located in the EXTRAM.
AUXR
Reset Value = xxxx xx00B
— —————EXTRAM AO
Not Bit Addressable
Bit:
Symbol Function
AO Disable/Enable ALE
AO Operating Mode
0 ALE is emitted at a constant rate of 1/6 the oscillator frequency.
1 ALE is active only during a MOVX or MOVC instruction.
EXTRAM Internal/External RAM access using MOVX @Ri/@DPTR
EXTRAM Operating Mode
0 Internal ERAM (00H–FFH) (00H–2FFH for RD+) access using MOVX @Ri/@DPTR
1 External data memory access.
— Not implemented, reserved for future use*.
NOTE:
*User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new
bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU01003
76543210
Address = 8EH
Figure 27. AUXR: Auxiliary Register (RX+ only)
