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LTC1929IG#PBF

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16
LTC1929/LTC1929-PG
Figure 5a. Secondary Output Loop with EXTV
CC
Connection Figure 5b. Capacitive Charge Pump for EXTV
CC
EXTV
CC
Connection
The LTC1929 contains an internal P-channel MOSFET
switch connected between the EXTV
CC
and INTV
CC
pins.
When the voltage applied to EXTV
CC
rises above
4.7V, the
internal regulator is turned off and the switch closes,
connecting the EXTV
CC
pin to the INTV
CC
pin thereby
supplying internal and MOSFET gate driving power. The
switch remains closed as long as the voltage applied to
EXTV
CC
remains above 4.5V. This allows the MOSFET
driver and control power to be derived from the output
during normal operation (4.7V < V
EXTVCC
< 7V) and from
the internal regulator when the output is out of regulation
(start-up, short-circuit). Do not apply greater than 7V to
the EXTV
CC
pin and ensure that EXTV
CC
< V
IN
+ 0.3V when
using the application circuits shown.
If an external voltage
source is applied to the EXTV
CC
pin when the V
IN
supply is
not present, a diode can be placed in series with the
LTC1929’s V
IN
pin and a Schottky diode between the
EXTV
CC
and the V
IN
pin, to prevent current from backfeeding
V
IN
.
Significant efficiency gains can be realized by powering
INTV
CC
from the output, since the V
IN
current resulting
from the driver and control currents will be scaled by the
ratio: (Duty Factor)/(Efficiency). For 5V regulators this
means connecting the EXTV
CC
pin directly to V
OUT
. How-
ever, for 3.3V and other lower voltage regulators, addi-
tional circuitry is required to derive INTV
CC
power from the
output.
The following list summarizes the four possible connec-
tions for EXTV
CC:
1. EXTV
CC
left open (or grounded). This will cause INTV
CC
to be powered from the internal 5V regulator resulting in
a significant efficiency penalty at high input voltages.
2. EXTV
CC
connected directly to V
OUT
. This is the normal
connection for a 5V regulator and provides the highest
efficiency.
3. EXTV
CC
connected to an external supply. If an external
supply is available in the 5V to 7V range, it may be used to
power EXTV
CC
providing it is compatible with the MOSFET
gate drive requirements.
4. EXTV
CC
connected to an output-derived boost network.
For 3.3V and other low voltage regulators, efficiency gains
can still be realized by connecting EXTV
CC
to an output-
derived voltage which has been boosted to greater than
4.7V but less than 7V. This can be done with either the
inductive boost winding as shown in Figure 5a or the
capacitive charge pump shown in Figure 5b. The charge
pump has the advantage of simple magnetics.
Topside MOSFET Driver Supply (C
B
,D
B
) (Refer to
Functional Diagram)
External bootstrap capacitors C
B1
and C
B2
connected to
the BOOST1 and BOOST2 pins supply the gate drive
voltages for the topside MOSFETs. Capacitor C
B
in the
Functional Diagram is charged though diode D
B
from
INTV
CC
when the SW pin is low. When the topside MOSFET
turns on, the driver places the C
B
voltage across the gate-
source of the desired MOSFET. This enhances the MOSFET
and turns on the topside switch. The switch node voltage,
APPLICATIO S I FOR ATIO
WUU
U
1929 F05a
V
IN
TG1
N-CH
1N4148
N-CH
BG1
PGND
LTC1929
SW1
EXTV
CC
OPTIONAL EXTV
CC
CONNECTION
5V < V
SEC
< 7V
T1
R
SENSE
V
SEC
V
OUT
V
IN
+
C
IN
+
1µF
+
C
OUT
17
LTC1929/LTC1929-PG
SW, rises to V
IN
and the BOOST pin rises to V
IN
+ V
INTVCC
.
The value of the boost capacitor C
B
needs to be 30 to 100
times that of the total input capacitance of the topside
MOSFET(s). The reverse breakdown of D
B
must be greater
than V
IN(MAX).
The final arbiter when defining the best gate drive ampli-
tude level will be the input supply current. If a change is
made that decreases input current, the efficiency has
improved. If the input current does not change then the
efficiency has not changed either.
Output Voltage
The LTC1929 has a true remote voltage sense capability.
The sensing connections should be returned from the load
back to the differential amplifier’s inputs through a com-
mon, tightly coupled pair of PC traces. The differential
amplifier rejects common mode signals capacitively or
inductively radiated into the feedback PC traces as well as
ground loop disturbances. The differential amplifier out-
put signal is divided down and compared with the internal
precision 0.8V voltage reference by the error amplifier.
The differential amplifier can be used in either of two
configurations according to the voltage applied to the
AMPMD pin (LTC1929 only). The first configuration, with
the connections illustrated in the Functional Diagram,
utilizes a set of internal precision resistors to enable
precision instrumentation-type measurement of the out-
put voltage. This configuration is activated when the
AMPMD pin is tied to ground and is the default for the
LTC1929-PG. When the AMPMD pin is tied to INTV
CC
, the
resistors are disconnected and the amplifier inputs are
made directly available. The amplifier can then be used as
a general purpose op amp. The amplifier has a 0V to 3V
common mode input range limitation due to the internal
switching of its inputs. The output is an NPN emitter
follower without any internal pull-down current. A DC
resistive load to ground is required in order to sink current.
The output will swing from 0V to 10V (V
IN
≥ V
DIFFOUT
+ 2V).
Soft-Start/Run Function
The RUN/SS pin provides three functions: 1) Run/Shut-
down, 2) soft-start and 3) a defeatable short-circuit latchoff
timer. Soft-start reduces the input power sources’ surge
currents by gradually increasing the controller’s current
limit I
TH(MAX)
. The latchoff timer prevents very short,
extreme load transients from tripping the overcurrent
latch. A small pull-up current (>5µA) supplied to the RUN/
SS pin will prevent the overcurrent latch from operating.
The following explanation describes how the functions
operate.
An internal 1.2µA current source charges up the C
SS
capacitor
.
When the voltage on RUN/SS reaches 1.5V, the
controller is permitted to start operating. As the voltage on
RUN/SS increases from 1.5V to 3.0V, the internal current
limit is increased from 25mV/R
SENSE
to 75mV/R
SENSE
.
The output current limit ramps up slowly, taking an
additional 1.4s/µF to reach full current. The output current
thus ramps up slowly, reducing the starting surge current
required from the input power supply. If RUN/SS has been
pulled all the way to ground there is a delay before starting
of approximately:
t
V
A
CsFC
DELAY SS SS
=
µ
=µ
()
15
12
125
.
.
./
The time for the output current to ramp up is then:
t
VV
A
CsFC
IRAMP SS SS
=
−
µ
=µ
()
315
12
125
.
.
./
By pulling both RUN/SS controller pins below 0.8V the
LTC1929 is put into low current shutdown (I
Q
< 40µA). The
RUN/SS pins can be driven directly from logic as shown in
Figure 6. Diode D1 in Figure 6 reduces the start delay but
allows C
SS
to ramp up slowly providing the soft-start
function. The RUN/SS pin has an internal 6V zener clamp
(see Functional Diagram).
Fault Conditions: Overcurrent Latchoff
The RUN/SS pin also provides the ability to latch off the
controllers when an overcurrent condition is detected.
The RUN/SS capacitor, C
SS
, is used initially to limit the
inrush current of both controllers. After the controllers
have been started and been given adequate time to charge
up the output capacitors and provide full load current, the
RUN/SS capacitor is used for a short-circuit timer. If the
output voltage falls to less than 70% of its nominal value,
APPLICATIO S I FOR ATIO
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18
LTC1929/LTC1929-PG
after C
SS
reaches 4.1V, C
SS
begins discharging on the
assump
tion that the output is in an overcurrent condition.
If the condition lasts for a long enough period as deter-
mined by the size of C
SS
, the controller will be shut down
until the RUN/SS pin voltage is recycled. If the overload
occurs during start-up, the time can be approximated by:
t
LO1
≈ (C
SS
• 0.6V)/(1.2µA) = 5 • 10
5
(C
SS
)
If the overload occurs after start-up the voltage on the
RUN/SS capacitor will continue charging and will provide
additional time before latching off:
t
LO2
≈ (C
SS
• 3V)/(1.2µA) = 2.5 • 10
6
(C
SS
)
This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor, R
SS
, to the RUN/SS pin as
shown in Figure 6. This resistance shortens the soft-start
period and prevents the discharge of the RUN/SS capaci-
tor during a severe overcurrent and/or short-circuit con-
dition. When deriving the 5µA current from V
IN
as in the
figure, current latchoff is always defeated. The diode
connecting of this pull-up resistor to INTV
CC
, as in
Figure␣ 6, eliminates any extra supply current during shut-
down while eliminating the INTV
CC
loading from prevent-
ing controller start-up.
Why should you defeat current latchoff? During the
prototyping stage of a design, there may be a problem with
noise pickup or poor layout causing the protection circuit
to latch off the controller. Defeating this feature allows
troubleshooting of the circuit and PC layout. The internal
short-circuit and foldback current limiting still remains
active, thereby protecting the power supply system from
failure. A decision can be made after the design is com-
plete whether to rely solely on foldback current limiting or
to enable the latchoff feature by removing the pull-up
resistor.
APPLICATIO S I FOR ATIO
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Figure 6. RUN/SS Pin Interfacing
The value of the soft-start capacitor C
SS
may need to be
scaled with output voltage, output capacitance and load
current characteristics. The minimum soft-start capaci-
tance is given by:
C
SS
> (C
OUT
)(V
OUT
)(10
-4
)(R
SENSE
)
The minimum recommended soft-start capacitor of C
SS
=
0.1µF will be sufficient for most applications.
Phase-Locked Loop and Frequency Synchronization
The LTC1929 has a phase-locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range of
the voltage controlled oscillator is ±50% around the
center frequency f
O
. A voltage applied to the PLLFLTR pin
of 1.2V corresponds to a frequency of approximately
220kHz. The nominal operating frequency range of the
LTC1929 is 140kHz to 310kHz.
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the
external and internal oscillators. This type of phase detec-
tor will not lock up on input frequencies close to the
harmonics of the VCO center frequency. The PLL hold-in
range, ∆f
H
, is equal to the capture range, ∆f
C:
∆f
H
= ∆f
C
= ±0.5 f
O
(150kHz-300kHz)
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLLFLTR pin. A simplified block
diagram is shown in Figure 7.
EXTERNAL
OSC
2.4V
R
LP
10k
C
LP
OSC
DIGITAL
PHASE/
FREQUENCY
DETECTOR
PHASE
DETECTOR
PLLIN
1929 F07
PLLFLTR
50k
Figure 7. Phase-Locked Loop Block Diagram
3.3V OR 5V RUN/SS
V
IN
INTV
CC
RUN/SS
D1
D1*
C
SS
R
SS
*
C
SS
R
SS
*
1929 F06
*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF
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LTC1929IG#PBF

Mfr. #:
Buy LTC1929IG#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Hi Pwr PolyPhase DC/DC Controllers
Lifecycle:
New from this manufacturer.
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