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MAX6892ETJ+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
MAX6892/MAX6893/MAX6894
Pin-Selectable, Octal/Hex/Quad, Power-Supply
Sequencers/Supervisors
_______________________________________________________________________________________ 7
PIN
MAX6892 MAX6893 MAX6894
NAME FUNCTION
1 1 1 PG2
Open-Drain, Power-Good Output 2. PG2 asserts low when the voltage input at
IN2 is below the pin-selectable/adjustable input threshold or ENABLE is pulled
high. PG2 deasserts with a factory preset timeout period of 6.25ms.
2 2 2 PG3
Open-Drain, Power-Good Output 3. PG3 asserts low when the voltage input at
IN3 is below the pin-selectable/adjustable input threshold or ENABLE is pulled
high. PG3 deasserts with a factory preset timeout period of 6.25ms.
3 3 3 PG4
Open-Drain, Power-Good Output 4. PG4 asserts low when the voltage input at
IN4 is below the pin-selectable/adjustable input threshold or ENABLE is pulled
high. PG4 deasserts with a factory preset timeout period of 6.25ms.
4 4 4 GND Ground
5 5 — PG5
Open-Drain, Power-Good Output 5. PG5 asserts low when the voltage input at
IN5 is below the pin-selectable/adjustable input threshold or ENABLE is pulled
high. PG5 deasserts with a factory preset timeout period of 6.25ms.
6 6 — PG6
Open-Drain, Power-Good Output 6. PG6 asserts low when the voltage input at
IN6 is below the pin-selectable/adjustable input threshold or ENABLE is pulled
high. PG6 deasserts with a factory preset timeout period of 6.25ms.
7 — — PG7
Open-Drain, Power-Good Output 7. PG7 asserts low when the voltage input at
IN7 is below the pin-selectable/adjustable input threshold or ENABLE is pulled
high. PG7 deasserts with a factory preset timeout period of 6.25ms.
8 — — PG8
Open-Drain, Power-Good Output 8. PG8 asserts low when the voltage input at
IN8 is below the pin-selectable/adjustable input threshold or ENABLE is pulled
high. PG8 deasserts with a factory preset timeout period of 6.25ms.
97 7RESET
Open-Drain, Active-Low Reset Output Stage. RESET asserts low when any
monitored input (IN_) is below the selected threshold or manual reset (MR) is
pulled low. RESET remains low for the reset timeout period after all reset-
causing conditions are cleared, and then deasserts.
10 8 8 WDO
Open-Drain, Active-Low Watchdog Output Stage. If WDI remains high or low for
longer than the watchdog timeout period, the internal watchdog timer runs out
and the WDO output asserts low. The internal watchdog timer clears whenever
RESET is asserted or WDI sees a rising or falling edge. Connect WDO to MR to
automatically assert the RESET output after each watchdog timeout fault.
11 9 9 MARGIN
Margin Input. MARGIN holds PG_, RESET, and WDO in their existing states
when driven low. Leave MARGIN unconnected or connect to DBP if unused.
MARGIN overrides MR if both assert at the same time. MARGIN is internally
pulled up to DBP through a 10µA current source.
12 10 10 MR
Active-Low Manual Reset Input. Pull MR low to assert RESET. RESET remains
asserted for its preset/adjustable reset timeout period when MR is driven/pulled
high. MR is internally pulled up to DBP through a 10µA current source.
13 11 11 TH0
Threshold Selection Input 0. Logic input to select desired thresholds. Connect
TH0 to GND or DBP. See Table 2 for available thresholds. Input has no internal
pullup or pulldown.
Pin Description
MAX6892/MAX6893/MAX6894
Pin-Selectable, Octal/Hex/Quad, Power-Supply
Sequencers/Supervisors
8 _______________________________________________________________________________________
Pin Description (continued)
PIN
MAX6892
MAX6893 MAX6894
NAME FUNCTION
14 12 12 TH1
Threshold Selection Input 1. Logic input to select desired thresholds. Connect
TH1 to GND or DBP. See Table 2 for available thresholds. Input has no internal
pullup or pulldown.
15 13 13 TH2
Threshold Selection Input 2. Logic input to select desired thresholds. Connect
TH2 to GND or DBP. See Table 2 for available thresholds. Input has no internal
pullup or pulldown.
16 14 14 TH3
Threshold Selection Input 3. Logic input to select desired thresholds. Connect
TH3 to GND or DBP. See Table 2 for available thresholds. Input has no internal
pullup or pulldown.
17 15 15 TH4
Threshold Selection Input 4. Logic input to select desired thresholds. Connect
TH4 to GND or DBP. See Table 2 for available thresholds. Input has no internal
pullup or pulldown.
18 16 16 SWT
Watchdog Timeout Adjust Input. Connect SWT to V
CC
to select the default
watchdog timeout period. Connect an external capacitor between SWT and
GND to adjust the watchdog timeout period. The adjustable timeout period is
calculated by t
WP
= 4.348E6 x C
SWT
(t
WP
in seconds and C
SWT
in Farads).
Disable the watchdog timer by connecting SWT to GND.
19 17 17 SRT
Reset Timeout Adjust Input. Connect SRT to V
CC
to select the default reset
timeout period. Connect an external capacitor between SRT and GND to adjust
the reset timeout period. The adjustable timeout period is calculated by t
RP
=
4.348E6 x C
SWT
(t
RP
in seconds and C
SRT
in Farads).
20 18 18
ENABLE
Active-Low, PG_ Enable Input. Pull ENABLE high to force all PG_ outputs low.
PG_ outputs remain asserted for their timeout period when ENABLE is
driven/pulled low. ENABLE is internally pulled down to GND through a 10µA
current sink.
21 19 19 V
CC
Internal Supply Voltage. Bypass V
CC
to GND with a 1µF capacitor as close to
the device as possible. V
CC
supplies power to the internal circuitry. V
CC
is
internally powered from the highest of the monitored IN2–IN5 voltages. Do not
use V
CC
to supply power to external circuitry. To externally supply V
CC,
see the
Powering the MAX6892/MAX6893/MAX6894 section.
22 20 20 DBP
Digital Bypass Voltage. DBP supplies power to the output stages. Bypass DBP
to GND with a 1µF capacitor as close to the device as possible. Do not use
DBP to supply power to external circuitry.
23 — — IN8
Input Voltage 8. Select undervoltage threshold using TH0–TH4. See Table 2.
For improved noise immunity, bypass IN8 to GND with a 0.1µF capacitor as
close to the device as possible.
24 — — IN7
Input Voltage 7. Select undervoltage threshold using TH0–TH4. See Table 2.
For improved noise immunity, bypass IN7 to GND with a 0.1µF capacitor as
close to the device as possible.
MAX6892/MAX6893/MAX6894
Pin Description (continued)
PIN
MAX6892 MAX6893 MAX6894
NAME FUNCTION
25 21 — IN6
Input Voltage 6. Select undervoltage threshold using TH0–TH4. See Table 2.
For improved noise immunity, bypass IN6 to GND with a 0.1µF capacitor as
close to the device as possible.
26 22 — IN5
Input Voltage 5. Select undervoltage threshold using TH0–TH4. See Table 2.
Power the device through IN2–IN5 or V
CC
(see the Powering the
MAX6892/MAX6893/MAX6894 section). For improved noise immunity, bypass
IN5 to GND with a 0.1µF capacitor as close to the device as possible.
27 23 23 IN4
Input Voltage 4. Select undervoltage threshold using TH0–TH4. See Table 2.
Power the device through IN2–IN5 or V
CC
(see the Powering the
MAX6892/MAX6893/MAX6894 section). For improved noise immunity, bypass
IN4 to GND with a 0.1µF capacitor as close to the device as possible.
28 24 24 IN3
Input Voltage 3. Select undervoltage threshold using TH0–TH4. See Table 2.
Power the device through IN2–IN5 or V
CC
(see the Powering the
MAX6892/MAX6893/MAX6894 section). For improved noise immunity, bypass
IN3 to GND with a 0.1µF capacitor as close to the device as possible.
29 25 25 IN2
Input Voltage 2. Select undervoltage threshold using TH0–TH4. See Table 2.
Power the device through IN2–IN5 or V
CC
(see the Powering the
MAX6892/MAX6893/MAX6894 section). For improved noise immunity, bypass
IN2 to GND with a 0.1µF capacitor as close to the device as possible.
30 26 26 IN1
Input Voltage 1. Select undervoltage threshold using TH0–TH4. See Table 2.
For improved noise immunity, bypass IN1 to GND with a 0.1µF capacitor as
close to the device as possible.
31 27 27 WDI
Watchdog Timer Input. Logic input for the watchdog timer function. If WDI is
not strobed with a valid low-to-high or high-to-low transition within the watchdog
timeout period, the watchdog output asserts low. The watchdog timeout period
is externally adjustable with capacitor C
SWT
or selectable for a fixed internal
timeout period. The watchdog has a long timeout period (92.16s minimum fixed
or 64x the adjusted short timeout period) after each reset event and a short
timeout period (1.44s minimum or an adjusted timeout period) after the first
valid WDI transition.
32 28 28 PG1
Open-Drain, Power-Good Output 1. PG1 asserts low when the voltage input at
IN1 is below the pin-selectable/adjustable input threshold or ENABLE is pulled
high. PG1 deasserts with a factory preset timeout period of 6.25ms.
— — 5, 6, 21, 22 N.C. No Connection. Not internally connected.
——— EP
Exposed Pad. Internally connected to GND. Connect EP to GND or leave
unconnected.
Pin-Selectable, Octal/Hex/Quad, Power-Supply
Sequencers/Supervisors
_______________________________________________________________________________________ 9
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

MAX6892ETJ+

Mfr. #:
Buy MAX6892ETJ+
Manufacturer:
Maxim Integrated
Description:
Supervisory Circuits Pin-Selectable Octal Power-Sup Sequencer
Lifecycle:
New from this manufacturer.
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