10
LTC1654
1654fb
OPERATIO
U
Table 1.
CONTROL
C3 C2 C1 C0
0000 Load Input Register n
0001 Update (Power-Up) DAC Register n
0010 Load Input Register n, Update (Power-Up) All
0011 Load and Update n
0100 Power Down n
0101 Fast n (Speed States are Maintained Even If DAC is
Put in Power-Down Mode)
0110 Slow n (Default State is Slow When Supplies are
Powered Up)
0111 Reserved (Do Not Use)
1000 Reserved (Do Not Use)
1001 Reserved (Do Not Use)
1010 Reserved (Do Not Use)
1011 Reserved (Do Not Use)
1100 Reserved (Do Not Use)
1101 Reserved (Do Not Use)
1110 Reserved (Do Not Use)
1111 No Operation
ADDRESS (n)
A3 A2 A1 A0
0000 DAC A
0001 DAC B
0010 Reserved (Do Not Use)
0011 Reserved (Do Not Use)
0100 Reserved (Do Not Use)
0101 Reserved (Do Not Use)
0110 Reserved (Do Not Use)
0111 Reserved (Do Not Use)
1000 Reserved (Do Not Use)
1001 Reserved (Do Not Use)
1010 Reserved (Do Not Use)
1011 Reserved (Do Not Use)
1100 Reserved (Do Not Use)
1101 Reserved (Do Not Use)
1110 Reserved (Do Not Use)
1111 Both DACs
INPUT WORD
C3
CONTROL ADDRESS DATA (14 + 2 DON'T CARE LSBs)
C2
C1
C0
A3
A2
A1
A0
D13
D12
D11 D10 D9 D8
D7
D6
D5 D4 D3 D2 D1
D0
X
X
1654 TABLE
11
LTC1654
1654fb
Rail-to-Rail Output Considerations
Rail-to-rail DACs take full advantage of the supply range
available to them, but cannot produce output voltages
above V
CC
or below ground. See Figure 2a.
If REFLO is tied to GND, the output for the lowest codes
may limit at 0V, as shown in Figure 2b. Similarly, limiting
can occur near full scale if the REFHI pin is tied to V
CC
, as
shown in Figure 2c.
The offset, gain error and linearity of the LTC1654 are
defined and tested in output ranges that avoid limiting.
The low code k
L
used in these measurements is defined as
the code which gives a nominal output of 32mV above
ground; see Table 2.
Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve: (a) Overall Transfer Function, (b) Effect of Negative
Offset for Codes Near Zero Scale, (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When V
REF
= V
CC
1654 F02
INPUT CODE
(b)
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
81920 16383
INPUT CODE
OUTPUT
VOLTAGE
(a)
V
REF
= V
CC
V
REF
= V
CC
(c)
INPUT CODE
OUTPUT
VOLTAGE
POSITIVE
FSE
APPLICATIO S I FOR ATIO
WUUU
Table 2. Low Code k
L
V
REFHI
, V
4.096 2.048
1 128 256
1/2 256 512
GAIN
Note: V
REFLO
= O
12
LTC1654
1654fb
Figure 3. Effect of Negative Offset
Least Significant Bit (LSB): One LSB is the ideal voltage
difference between two successive codes.
LSB = (V
FS
– V
OS
)/(2
n
– 1) = (V
FS
– V
OS
)/16383
Nominal LSBs:
LTC1654 LSB = 4.09575V/16383 = 250µV
Zero-Scale Error (ZSE): The output voltage when the
DAC is loaded with all zeros. Since this is a single supply
part, this value cannot be less than 0V.
Integral Nonlinearity (INL): End-point INL is the maxi-
mum deviation from a straight line passing through the
end points of the DAC transfer curve. Because the part
operates from a single supply and the output cannot go
below zero, the linearity is measured between low code
k
L
and full scale. The INL error at a given input code is
calculated as follows:
INL = [V
OUT
– V
OS
– (V
FS
– V
OS
)(code/16383)]/LSB
V
OUT
= The output voltage of the DAC measured at the
given input code
Differential Nonlinearity (DNL): DNL is the difference
between the measured change and the ideal one LSB
change between any two adjacent codes. The DNL error
between any two codes is calculated as follows:
DNL = (V
OUT
– LSB)/LSB
V
OUT
= The measured voltage difference between
two adjacent codes
Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
nV • s.
Resolution (n): Resolution is defined as the number of
digital input bits (n). It is also the number of DAC output
states (2
n
) that divide the full-scale range. Resolution does
not imply linearity.
Full-Scale Voltage (V
FS
): This is the output of the DAC
when all bits are set to 1.
Voltage Offset Error (V
OS
): Normally, DAC offset is the
voltage at the output when the DAC is loaded with all zeros.
The DAC can have a true negative offset, but because the
part is operated from a single supply, the output cannot go
below 0V. If the offset is negative, the output will remain
near 0V resulting in the transfer curve shown in Figure 3.
Therefore, the offset of the part is measured at low code k
L
:
V
Vk
kV
k
OS
OUT
L
L
FS
n
L
n
=
()
()( )
21
1
21
DAC CODE
1654 F01
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
DEFI ITIO S
UU

LTC1654IGN#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 2x 14-B R2R DAC in 16-Lead SSOP Package
Lifecycle:
New from this manufacturer.
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