LTC3707-SYNC
25
3707sfa
Design Example
As a design example for one channel, assume V
IN
=
12V(nominal), V
IN
= 22V(max), V
OUT
= 1.8V, I
MAX
= 5A,
and f = 300kHz.
The inductance value is chosen fi rst based on a 30% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the PLLFLTR
pin to the INTV
CC
pin for 300kHz operation. The minimum
inductance for 30% ripple current is:
ΔI
V
fL
V
V
L
OUT OUT
IN
=
()( )
1
A 4.7μH inductor will produce 23% ripple current and a
3.3μH will result in 33%. The peak inductor current will be
the maximum DC value plus one half the ripple current, or
5.84A, for the 3.3μH value. Increasing the ripple current
will also help ensure that the minimum on-time of 200ns
is not violated. The minimum on-time occurs at maximum
V
IN
:
t
V
Vf
V
VkHz
n
ON MIN
OUT
IN MAX
()
()
.
()
== =
18
22 300
273 ss
The R
SENSE
resistor value can be calculated by using the
maximum current sense voltage specifi cation with some
accommodation for tolerances:
R
mV
A
SENSE
≤≈Ω
60
584
001
.
.
Since the output voltage is below 2.4V the output resis-
tive divider will need to be sized to not only set the output
voltage but also to absorb the SENSE pins specifi ed input
current.
Rk
V
VV
K
V
VV
k
MAX
OUT
124
08
24
24
08
24 18
32
()
.
.–
.
.–.
=
=
=
Choosing 1% resistors; R1 = 25.5k and R2 = 32.4k yields
an output voltage of 1.816V.
APPLICATIONS INFORMATION
The power dissipation on the top side MOSFET can be
easily estimated. Choosing a Fairchild FOS6982S results
in; R
DS(ON)
= 0.035Ω/0.022Ω, calculated C
MILLER
is
3nC/15V = 200pF. At maximum input voltage with
T(estimated) = 50°C:
P
V
V
CC
MAIN
=
()
°
[]
18
22
5 1 0 005 50 25 0 03
2
.
(. )( ) .
55
1
2
22 5 4 200
1
52
1
2
3
2
Ω
()
+
()()
Ω
()( )
+
VA pF
000
323
kHz
mW
()
=
A short-circuit to ground will result in a folded back
current of:
I
mV ns V
µH
A
SC
=
Ω
+
=
25
001
1
2
200 22
33
32
.
()
.
.
with a typical value of R
DS(ON)
and δ = (0.005/°C)(20) = 0.1.
The resulting power dissipated in the bottom MOSFET is:
P
VV
V
A
mW
SYNC
=
()()
Ω
()
=
22 1 8
22
32 11 0022
227
2
–.
...
which is less than under full-load conditions.
C
IN
is chosen for an RMS current rating of at least 3A at
temperature assuming only this channel is on. C
OUT
is
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
V
ORIPPLE
= R
ESR
(ΔI
L
) = 0.02Ω(1.67A) = 33mV
P–P
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 10. The Figure 11 illustrates the
current waveforms present in the various branches of the
2-phase synchronous regulators operating in the continu-
ous mode. Check the following in your layout:
LTC3707-SYNC
26
3707sfa
1. Are the top N-channel MOSFETs M1 and M3 located
within 1cm of each other with a common drain connection
at C
IN
? Do not attempt to split the input decoupling for
the two channels as it can cause a large resonant loop.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of C
INTVCC
must return to the combined C
OUT
(–) terminals.
The path formed by the top N-channel MOSFET, Schottky
diode and the C
IN
capacitor should have short leads and PC
trace lengths. The output capacitor (–) terminals should be
connected as close as possible to the (–) terminals of the
input capacitor by placing the capacitors next to each other
and away from the Schottky loop described above.
3. Do the IC V
OSENSE
pins resistive dividers connect to
the (+) terminals of C
OUT
? The resistive divider must be
APPLICATIONS INFORMATION
connected between the (+) terminal of C
OUT
and signal
ground. The R2 and R4 connections should not be along
the high current input feeds from the input capacitor(s).
4. Are the SENSE
and SENSE
+
leads routed together with
minimum PC trace spacing? The fi lter capacitor between
SENSE
+
and SENSE
should be as close as possible to the
IC. Ensure accurate current sensing with Kelvin connections
at the SENSE resistor.
5. Is the INTV
CC
decoupling capacitor connected close to
the IC, between the INTV
CC
and the power ground pins?
This capacitor carries the MOSFET drivers current peaks.
An additional 1μF ceramic capacitor placed immediately
next to the INTV
CC
and PGND pins can help improve noise
performance substantially.
Figure 10. LTC3707-SYNC Recommended Printed Circuit Layout Diagram
C
B2
C
B1
R
PU
PGOOD
V
PULL-UP
(<7V)
C
INTVCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+
C
IN
D1
M1 M2
M3 M4
D2
+
C
VIN
V
IN
R
IN
INTV
CC
3.3V
R4R3
R2
R1
RUN/SS1
SENSE1
+
SENSE1
V
OSENSE1
PLLFLTR
PLLIN
FCB
I
TH1
SGND
3.3V
OUT
I
TH2
V
OSENSE2
SENSE2
SENSE2
+
PGOOD
TG1
SW1
BOOST1
V
IN
BG1
EXTV
CC
INTV
CC
PGND
BG2
BOOST2
SW2
TG2
RUN/SS2
LTC3707-SYNC
L1
L2
C
OUT1
V
OUT1
GND
V
OUT2
3707 F10
+
C
OUT2
+
R
SENSE
R
SENSE
f
IN
LTC3707-SYNC
27
3707sfa
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2), and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from the
opposites channel’s voltage and current sensing feedback
pins. All of these nodes have very large and fast moving
signals and therefore should be kept on the “output side”
of the IC and occupy minimum PC trace area.
7. Use a modifi ed “star ground” technique: a low impedance,
large copper area central grounding point on the same side
of the PC board as the input and output capacitors with
tie-ins for the bottom of the INTV
CC
decoupling capacitor,
the bottom of the voltage feedback resistive divider and
the SGND pin of the IC.
APPLICATIONS INFORMATION
PC Board Layout Debugging
Start with one controller on at a time. It is helpful to use
a DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output voltage
as well. Check for proper performance over the operating
voltage and current range expected in the application. The
frequency of operation should be maintained over the input
voltage range down to dropout and until the output load
drops below the low current operation threshold—typically
10% to 20% of the maximum designed current level in
Burst Mode operation.
Figure 11. Branch Current Waveforms
R
L1
D1
L1
SW1
R
SENSE1
V
OUT1
C
OUT1
+
V
IN
C
IN
R
IN
+
R
L2
D2
BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH.
L2
SW2
3707 F11
R
SENSE2
V
OUT2
C
OUT2
+

LTC3707IGN-SYNC#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator
Lifecycle:
New from this manufacturer.
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