REVISION A 9/25/15
843022I-48 DATA SHEET
7 FEMTOCLOCKS™ CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK GENERATOR
APPLICATION INFORMATION
FIGURE 2. CRYSTAL INPUt INTERFACE
CRYSTAL INPUT INTERFACE
The 843022I-48 has been characterized with 18pF parallel resonant
crystals. The capacitor values, C1 and C2, shown in Figure 2 below
were determined using a 25MHz, 18pF parallel resonant crystal and
were chosen to minimize the ppm error. The optimum C1 and C2
values can be slightly adjusted for different board layouts.
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The 843022I-48 provides
separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. V
CC
and V
CCA
should be
individually connected to the power supply plane through
vias, and bypass capacitors should be used for each pin. To
achieve optimum jitter performance, power supply isolation is re-
quired. Figure 1 illustrates how a 10Ω resistor along with a 10μF
and a .01μF bypass capacitor should be connected to each V
CCA
pin.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 1. POWER SUPPLY FILTERING
10Ω
V
CCA
10 μF
.01μF
3.3V or 2.5V
.01μF
V
CC
