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VF2510BGLFT

P1-P3P4-P6P7-P7
Integrated
Circuit
Systems, Inc.
General Description Features
ICSVF2510
0722A—05/07/03
Block Diagram
3.3V Phase-Lock Loop Clock Driver
Pin Configuration
The ICSVF2510 is a high performance, low skew, low jitter
clock driver. It uses a phase lock loop (PLL) technology to
align, in both phase and frequency, the CLKIN signal with
the CLKOUT signal. It is specifically designed for use with
synchronous SDRAMs. The ICSVF2510 operates at 3.3V
VCC and drives up to ten clock loads.
One bank of ten outputs provide low-skew, low-jitter
copies of CLKIN. Output signal duty cycles are adjusted
to 50 percent, independent of the duty cycle at CLKIN.
Outputs can be enabled or disabled via control (OE)
inputs. When the OE inputs are high, the outputs align in
phase and frequency with CLKIN; when the OE inputs are
low, the outputs are disabled to the logic low state.
The ICSVF2510 does not require external RC filter
components. The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost. The
test mode shuts off the PLL and connects the input
directly to the output buffer. This test mode, the ICSVF2510
can be use as low skew fanout clock buffer device. The
ICSVF2510 comes in 24 pin 173mil Thin Shrink Small-
Outline package (TSSOP) package.
• Meets or exceeds PC133 registered DIMM
specification1.1
• Spread Spectrum Clock Compatible
• Distributes one clock input to one bank of ten outputs
• Operating frequency 20MHz to 200MHz
• External feedback input (FBIN) terminal is used to
synchrionize the outputs to the clock input
• No external RC network required
• Operates at 3.3V Vcc
• Plastic 24-pin 173mil TSSOP package
FBIN
CLKIN
AVCC
OE
PLL
CLK1
CLK0
FBOUT
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
AGND 1 24 CLKIN
VCC 2 23 AVCC
CLK0 3 22 VCC
CLK1 4 21 CLK9
CLK2 5 20 CLK8
GND 6 19 GND
GND 7 18 GND
CLK3 8 17 CLK7
CLK4 9 16 CLK6
VCC 10 15 CLK5
OE 11 14 VCC
FBOUT 12 13 FBIN
24 Pin TSSOP
4.40 mm. Bod
y
, 0.65 mm. Pitch
ICSVF2510
2
ICSVF2510
0722A—05/07/03
Pin Descriptions
Note:
1. Weak pull-ups on these inputs
Functionality
PIN # PIN NAME TYPE DESCRIPTION
1 AGND PWR Analog Ground
2, 10, 14 VCC PWR Power Supply (3.3V)
3 CLK0 OUT Buffered clock output.
4 CLK1 OUT Buffered clock output.
5 CLK2 OUT Buffered clock output.
6, 7, 18, 19 GND PWR Ground
8 CLK3 OUT Buffered clock output.
9 CLK4 OUT Buffered clock output.
11
OE
1
IN
Output enable (has internal pull_up). When high, normal operation.
When low, clock outputs are disabled to a logic low state.
12 FBOUT OUT Feedback output
13 FBIN IN Feedback input
15 CLK5 OUT Buffered clock output.
16 CLK6 OUT Buffered clock output.
17 CLK7 OUT Buffered clock output.
20 CLK8 OUT Buffered clock output.
21 CLK9 OUT Buffered clock output.
22 VCC PWR Power Supply (3.3V) digital supply.
23 AVCC IN
Analog power supply (3.3V). When input is ground PLL is off and
bypassed.
24 CLKIN IN Clock input
OE AVCC CLK (9:0) FBOUT Source
03.33 0DrivenPLLN
1 3.33 Driven Driven PLL N
00 0DrivenCLKINY
10
Driven
Driven CLKIN Y
Test mode:
When AVCC is 0, shuts off the PLL
and connects the input directly to the output buffers
Buffer Mode
INPUTS OUTPUTS
PLL
Shutdown
3
ICSVF2510
0722A—05/07/03
Absolute Maximum Ratings
Supply Voltage (AVCC). . . . . . . . . . . . . . . . . AVCC < (V
cc
+ 0.7 V)
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . 4.3 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V
cc
+ 0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - OUTPUT
T
A
= 0 - 70°C; V
DD
= V
DDL
= 3.3 V +/-10%; C
L
= 30 pF; R
L
= 500 Ohms (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Voltage V
OH
I
OH
= -8 mA 2.4 2.9 V
Output Low Voltage V
OL
I
OL
= 8 mA 0.25 0.4 V
V
OH
= 2.4 V 27
V
OH
= 2.0 V 39
V
OL
= 0.8 V 26
V
OL
= 0.55 V 19
Rise Time
1
T
r
V
OL
= 0.8 V, V
OH
= 2.0 V 0.5 1.1 2.1 ns
Fall Time
1
T
f
V
OH
= 2.0 V, V
OL
= 0.8 V 0.5 1.1 2.7 ns
Duty Cycle
1
D
t
V
T
= 1.5 V;C
L
=30 pF 48 50 52 %
Cycle to Cycle jitter
1
T
CY
C
- T
CY
C
at 66-100 MHz ; loaded outputs 75
ps
Absolute Jitter
1
T
JABS
10000 cycles; C
L
= 30 pF 100 ps
Skew
1
T
sk
V
T
= 1.5 V (Window) Output to Output 100 ps
Phase error
1
T
p
e
V
T
= Vdd/2; CLKIN-FBIN -75 75 ps
Delay Input-Output
1
D
R1
V
T
= 1.5 V; PLL_EN = 0
3.3 3.7 ns
1
Guaranteed by design, not 100% tested in production.
mA
mA
Output High Current
Output Low Current
I
OH
I
OL
P1-P3P4-P6P7-P7

VF2510BGLFT

Mfr. #:
Buy VF2510BGLFT
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 3.3V Phase-Lock Loop Clock Driver
Lifecycle:
New from this manufacturer.
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