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74LVTH322373GX

P1-P3P4-P6
© 2002 Fairchild Semiconductor Corporation DS500742 www.fairchildsemi.com
May 2002
Revised May 2002
74LVT322373 • 74LVTH322373 Low Voltage 32-Bit Transparent Latch with 3-STATE Outputs and 25
Ω
Series
Resistors in the Outputs
74LVT322373 • 74LVTH322373
Low Voltage 32-Bit Transparent Latch
with 3-STATE Outputs
and 25
Ω Series Resistors in the Outputs
General Description
The LVT322373 and LVTH322373 contain thirty-two non-
inverting latches with 3-STATE outputs and are intended
for bus oriented applications. The device is byte controlled.
The flip-flops appear transparent to the data when the
Latch Enable (LE) is HIGH. When LE is LOW, the data that
meets the setup time is latched. Data appears on the bus
when the Output Enable (OE
) is LOW. When OE is HIGH,
the outputs are in a high impedance state.
The LVTH322373 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These latches are designed for low voltage (3.3V) V
CC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVT322373 and
LVTH322373 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining a low power dissipation.
Features
■ Input and output interface capability to systems at
5V V
CC
■ Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH322373),
also available without bushold feature (74LVT322373)
■ Live insertion/extraction permitted
■ Power Up/Down high impedance provides glitch-free
bus loading
■ Outputs include equivalent series resistance of 25
Ω to
make external termination resistors unnecessary and
reduce overshoot and undershoot
■ ESD performance:
Human-body model
> 2000V
Machine model
> 200V
Charged-device model
> 1000V
■ Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Ordering Code:
Note 1: Ordering Code “G” indicates Trays.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Order Number Package Number Package Description
74LVT322373G
(Note 1) (Note 2)
BGA96A
(Preliminary)
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74LVTH322373G
(Note 1) (Note 2)
BGA96A 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
www.fairchildsemi.com 2
74LVT322373 • 74LVTH322373
Connection Diagram
(Top Thru View)
Pin Descriptions
FBGA Pin Assignments
Truth Table
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance O
o
= Previous O
o
prior to HIGH-to-LOW transition of LE
Functional Description
The LVT322373 and LVTH322373 contain thirty-two D-type latches with 3-STATE standard outputs. The device is byte con-
trolled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full
32-bit operation. The following description applies to each byte. When the Latch Enable (LE
n
) input is HIGH, data on the D
n
enters the latches. In this condition the latches are transparent, i.e, a latch output will change states each time its D input
changes. When LE
n
is LOW, the latches store information that was present on the D inputs a setup time preceding the
HIGH-to-LOW transition of LE
n
. The 3-STATE standard outputs are controlled by the Output Enable (OE
n
) input. When OE
n
is LOW, the standard outputs are in the 2-state mode. When OE
n
is HIGH, the standard outputs are in the high impedance
mode but this does not interfere with entering new data into the latches.
Pin Names Description
OE
n
Output Enable Input (Active LOW)
LE
n
Latch Enable Input
I
0
–I
31
Inputs
O
0
–O
31
3-STATE Outputs
123456
A O
1
O
0
OE
1
LE
1
I
0
I
1
B O
3
O
2
GND GND I
2
I
3
C O
5
O
4
V
CC1
V
CC1
I
4
I
5
D O
7
O
6
GND GND I
6
I
7
E O
9
O
8
GND GND I
8
I
9
F O
11
O
10
V
CC1
V
CC1
I
10
I
11
G O
13
O
12
GND GND I
12
I
13
H O
14
O
15
OE
2
LE
2
I
15
I
14
J O
17
O
16
OE
3
LE
3
I
16
I
17
K O
19
O
18
GND GND I
18
I
19
L O
21
O
20
V
CC2
V
CC2
I
20
I
21
M O
23
O
22
GND GND I
22
I
23
N O
25
O
24
GND GND I
24
I
25
P O
27
O
26
V
CC2
V
CC2
I
26
I
27
R O
29
O
28
GND GND I
28
I
29
T O
30
O
31
OE
4
LE
4
I
31
I
30
Inputs Outputs Inputs Outputs
LE
1
OE
1
I
0
–I
7
O
0
–O
7
LE
2
OE
2
I
8
–I
15
O
8
–O
15
XH X Z XHX Z
HL L L HLL L
HL H H HLH H
LL X O
0
LLX O
0
Inputs Outputs Inputs Outputs
LE
3
OE
3
I
16
–I
23
O
16
–O
23
LE
4
OE
4
I
24
–I
31
O
24
–O
31
XH X Z XHX Z
HL L L HLL L
HL H H HLH H
LL X O
0
LLX O
0
3 www.fairchildsemi.com
74LVT322373 • 74LVTH322373
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
Byte 3 (16:23)
Byte 4 (24:31)
V
CC1
is associated with Bytes 1 and 2.
V
CC2
is associated with Bytes 3 and 4.
Note: Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
P1-P3P4-P6

74LVTH322373GX

Mfr. #:
Buy 74LVTH322373GX
Manufacturer:
ON Semiconductor
Description:
IC LATCH TRANSP 32BIT 3ST 96FBGA
Lifecycle:
New from this manufacturer.
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