LTC4089/LTC4089-5
19
40895fc
Increasing R
NOM
will move both trip points to lower
temperatures. Likewise, a decrease in R
NOM
with respect
to R
NTC
will move the trip points to higher temperatures.
To calculate R
NOM
for a shift to lower temperature, for
example, use the following equation:
R
R
RatC
NOM
COLD
NTC
2 815
25
.
where R
COLD
is the resistance ratio of R
NTC
at the desired
cold temperature trip point. To shift the trip points to higher
temperatures use the following equation:
R
R
RatC
NOM
HOT
NTC
0 4086
25
.
where R
HOT
is the resistance ratio of R
NTC
at the desired
hot temperature trip point.
The following example uses a 100K R-T Curve 1 Thermistor
from Vishay Dale. The difference between the trip points is
44°C, from before—and the desired cold trip point of 0°C,
would put the hot trip point at 44°C. The R
NOM
needed is
calculated as follows:
R
R
RatC
NOM
COLD
NTC
=
2 815
25
3 266
2 815
100
.
.
.
•kkkΩΩ=116
The nearest 1% value for R
NOM
is 115k. This is the value
used to bias the NTC thermistor to get cold and hot trip
points of approximately 0°C and 44°C, respectively. To
extend the delta between the cold and hot trip points,
a resistor (R1) can be added in series with R
NTC
(see
Figure 7). The values of the resistors are calculated as
follows:
R
RR
R
NOM
COLD HOT
=
=
2 815 0 4086
1
0 4086
2 815 0
..
.
.
..
4086
[]
RRR
COLD HOT HOT
where R
NOM
is the value of the bias resistor, R
HOT
and
R
COLD
are the values of R
NTC
at the desired temperature
trip points. Continuing the forementioned example with
a desired hot trip point of 50°C:
R
RR
k
NOM
COLD HOT
=
=
2 815 0 4086
100 3 266 0 3
..
•( . .
6602
2 815 0 4086
120 8 121 1
110
)
..
., %
=
=
k k nearest
R
00
0 4086
2 815 0 4086
3 266 0 3602
k•
.
..
..
()
=
0 3602
13 3 13 3 1
.
., . %k k is nearest
The fi nal solution is shown in Figure 7, where
R
NOM
= 121k, R1 = 13.3k and R
NTC
= 100k at 25°C
Figure 7. Modifi ed NTC Circuit
APPLICATIONS INFORMATION
+
+
R
NOM
121k
R
NTC
100k
R1
13.3k
NTC
VNTC
15
0.1V
NTC_ENABLE
4089 F07
TOO_COLD
TOO_HOT
0.74 •
VNTC
0.29 • VNTC
+
14
LTC4089
LTC4089/LTC4089-5
20
40895fc
Power Dissipation and High Temperature
Considerations
The die temperature of the LTC4089/LTC4089-5 must
be lower than the maximum rating of 110°C. This is
generally not a concern unless the ambient temperature
is above 85°C. The total power dissipated inside the
LTC4089/LTC4089-5 depends on many factors, including
input voltage (IN or HVIN), battery voltage, programmed
charge current, programmed input current limit, and load
current.
In general, if the LTC4089/LTC4089-5 is being powered from
IN the power dissipation can be calculated as follows:
PVV I VV I
D IN BAT BAT IN OUT OUT
=− +()()
where P
D
is the power dissipated, I
BAT
is the battery
charge current, and I
OUT
is the application load current.
For a typical application, an example of this calculation
would be:
PVV AV VA
mW
D
=− + =(.).(.).53704 547501
545
This example assumes V
IN
= 5V, V
OUT
= 4.75V, V
BAT
= 3.7V,
I
BAT
= 400mA, and I
OUT
= 100mA resulting in slightly more
than 0.5W total dissipation.
If the LTC4089 is being powered from HVIN, the power
dissipation can be estimated by calculating the regulator
power loss from an effi ciency measurement, and subtract-
ing the catch diode loss.
PVIIV
V
V
D HVOUT BAT OUT D
HVOUT
H
=− +
( )•( •( )) 1
1
η
VVIN
BAT OUT BAT
II VI
++•( ) . 03
where is the effi ciency of the high voltage regulator
and V
D
is the forward voltage of the catch diode at I =
I
BAT
+ I
OUT
. The fi rst term corresponds to the power lost
in converting V
HVIN
to V
HVOUT
, the second term subtracts
the catch diode loss, and the third term is the power
dissipated in the battery charger. For a typical application,
an example of this calculation would be:
PVAAV
V
V
D
=− +
[]
( . )• •( . . ) . 1087 4 07 03 04
1
4
12
++ =•( . . ) . .07 03 03 07 463AA VA mW
This example assumes 87% effi ciency, V
HVIN
= 12V, V
BAT
=
3.7V (V
HVOUT
is about 4V), I
BAT
= 700mA, I
OUT
= 300mA
resulting in less than 0.5W total dissipation.
If the LTC4089-5 is being powered from HVIN, the power
dissipation can be estimated by calculating the regulator
power loss from an effi ciency measurement and subtract-
ing the catch diode loss.
PVII
V
V
V
D BAT OUT
D
HVIN
=− +
−−
( )•( •( ))
15
1
5
η
+
+−
•( )
()
II
VV I
BAT OUT
BAT BAT
5
The difference between this equation and the LTC4089 is
the last term which represents the power dissipation in
the battery charger. For a typical application, an example
of this calculation would be:
PVAA
V
V
V
D
=− +
−−
(.)((. .))
.•( )
1 0 87 5 0 7 0 3
04 1
5
12
•( . . )
(.).,
07 03
537071327
AA
VVA mW
+
+− =
Like the LTC4089 example, this example assumes 87%
effi ciency, V
HVIN
= 12V, V
BAT
= 3.7V, I
BAT
= 700mA, I
OUT
=
300mA resulting in 1.3W total dissipation.
To prevent power dissipation of this magnitude from
causing high die temperature, it is important to solder the
exposed backside of the package to a ground plane. This
ground should be tied to other copper layers below with
thermal vias; these layers will spread the heat dissipated
by the LTC4089. Additional vias should be placed near the
catch diodes. Adding more copper to the top and bottom
layers, and tying this copper to the internal planes with
vias, can reduce thermal resistance further. With these
steps, the thermal resistance from die (i.e., junction) to
ambient can be reduced to
JA
= 40°C/W.
APPLICATIONS INFORMATION
LTC4089/LTC4089-5
21
40895fc
The power dissipation in the other power compo-
nents—catch diodes, MOSFETs, boost diodes and induc-
tors—causes additional copper heating and can further
increase the “ambient” temperature of the IC.
Board Layout Considerations
As discussed in the previous section, it is critical that
the exposed metal pad on the backside of the LTC4089/
LTC4089-5 package be soldered to the PC board ground.
Furthermore, proper operation and minimum EMI requires
a careful printed circuit board (PCB) layout. Note that large,
switched currents fl ow in the power switch (between the
HVIN and SW pins), the catch diode and the HVIN input
capacitor. These components, along with the inductor and
output capacitor, should be placed on the same side of
the circuit board, and their connections should be made
on that layer. Place a local, unbroken ground plane below
these components. The loop formed by these components
should be as small as possible. Additionally, the SW and
BOOST nodes should be kept as small as possible. Figure 8
shows the recommended component placement with trace
and via locations.
High frequency currents, such as the high voltage input
current of the LTC4089, tend to fi nd their way along
the ground plane on a mirror path directly beneath the
incident path on the top of the board. If there are slits or
cuts in the ground plane due to other traces on that layer,
the current will be forced to go around the slits. If high
frequency currents are not allowed to fl ow back through
their natural least-area path, excessive voltage will build
up and radiated emissions will occur. See Figure 9.
Figure 8. Suggested Board Layout
Figure 9. Ground Currents Follow Their Incident Path
at High Speed. Slices in the Ground Plane Cause High
Voltage and Increased Emissions.
MINIMIZE D1, L1,
C3, U1, SW PIN LOOP
MINIMIZE TRACE LENGTH
U1 THERMAL PAD
SOLDERED TO PCB.
VIAS CONNECTED TO ALL
GND PLANES WITHOUT
THERMAL RELIEF.
C1 AND D1
GND PADS
SIDE-BY-SIDE
AND SEPERATED
WITH C3 GND PAD
APPLICATIONS INFORMATION
V
IN
and V
HVIN
Bypass Capacitor
Many types of capacitors can be used for input bypassing,
however, caution must be exercised when using multilayer
ceramic capacitors. Because of the self-resonant and high
Q characteristics of some types of ceramic capacitors,
high voltage transients can be generated under some
start-up conditions, such as from connecting the charger
input to a hot power source. For more information, refer
to Application Note 88.
Battery Charger Stability Considerations
The constant-voltage mode feedback loop is stable without
any compensation when a battery is connected with low
impedance leads. Excessive lead length, however, may add
enough series inductance to require a bypass capacitor
of at least 1μF from BAT to GND. Furthermore, a 4.7μF
capacitor with a 0.2 to 1 series resistor to GND is
recommended at the BAT pin to keep ripple voltage low
when the battery is disconnected.
4089 F09

LTC4089EDJC#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management USB Power Manager and Li-Ion Charger
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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