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TDA7442D013TR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
TDA7442 - TDA7442D
4/17
TREBLE CONTROL
G
t
Control Range Max. Boost/cut +13.0 +14.0 +15.0 dB
T
STEP
Step Resolution 1 2 3 dB
EFFECT CONTROL
C
RANGE
Control Range - 21 - 6 dB
S
STEP
Step Resolution 0.5 1 1.5 dB
SURROUND SOUND MATRIX PHASE
R
PS10
Phase Shifter 1: D1 = 0, D0 = 0
8.3 11.8 15.2 KΩ
R
PS11
Phase Shifter 1: D1 = 0, D0 = 1
10 14.1 18.3 KΩ
R
PS12
Phase Shifter 1: D1 = 1, D0 = 0
12.6 17.9 23.3 KΩ
R
PS13
Phase Shifter 1: D1 = 1, D0 = 1
26.4 37.3 48.85 KΩ
SURROUND SOUND MATRIX
TEST CONDITION (Phase Resistor Selection D0=0, D1=1, D2=0. D3=1, D4=0, D5=1, D6=0, D7=1
G
OFF
In-phase Gain (OFF) Mode OFF, Input signal of
1kHz, 1.4 V
p-p
, R
in
→ R
out
L
in
→
L
out
-1 0 1 dB
D
GOFF
LR In-phase Gain Difference
(OFF)
Mode OFF, Input signal of 1kHz,
1.4 V
p-p
R
in
→ R
out
, L
in
→ L
ou
t
-1 0 1 dB
G
MUS
In-phase Gain (Music) Music mode, Effect Ctrl = -6dB
Input signal of 1kHz, 1.4 V
p-p
(R
in
→ R
out
), (L
in
→ L
out
)
7dB
D
GMUS
LR In-phase Gain Difference
(Music)
Music mode, Effect Ctrl = -6dB
Input signal of 1kHz, 1.4 V
p-p
(R
in
→ R
out
) - (L
in
→ L
out
)
0dB
SPEAKER ATTENUATORS
C
range
Control Range 79 dB
S
STEP
Step Resolution -0.5 1 1.5 dB
E
A
Attenuation set error Av = 0 to -20dB -1.5 0 1.5 dB
Av = -20 to -79dB -3 0 2 dB
V
DC
DC Steps adjacent att. steps -3 0 3 mV
A
MUTE
Output Mute Condition +70 100 dB
R
VEA
Input Impedance 21 30 39 KΩ
AUDIO OUTPUTS
N
O(OFF)
Output Noise (OFF) Output Mute, Flat
B
W
= 20Hz to 20KHz
4
5
µVrms
µVrms
N
O(MUS)
Output Noise (Music) Mode = Music ,
B
W
= 20Hz to 20KHz,
30 mVrms
N
O(PSEUDO)
Output Noise (Pseudo Stereo) Mode = Pseudo Stereo
B
W
= 20Hz to 20KHz,
30 mVrms
d Distorsion Av = 0 ; V
in
= 1Vrms 0.01 0.1 %
S
C
Channel Separation 70 90 dB
V
OCL
Clipping Level d = 0.3% 2 2.5 Vrms
R
OUT
Output Resistance 10 30 50 Ω
Table 5. Electrical Characteristics (continued)
Refer to the test circuit T
amb
= 25°C, V
S
= 9V, R
L
= 10KΩ, V
in
= 1Vrms; R
G
= 600Ω, all controls flat (G =
0dB), Effect Ctrl = -6dB, MODE = OFF; f = 1KHz unless otherwise specified.
Symbol Parameter Test Condition Min. Typ. Max. Unit
5/17
TDA7442 - TDA7442D
V
OUT
DC Voltage Level 3.8 V
MONITOR OUTPUTS
d Distorsion Av = 0 ; V
in
= 1Vrms 0.01 0.1 %
S
C
Channel Separation 70 90 dB
V
OCL
Clipping Level d = 0.3% 2 2.5 Vrms
R
OUT
Output Resistance 20 50 70 Ω
V
OUT
DC Voltage Level 4.5 V
BUS INPUTS
V
IL
Input Low Voltage 1V
V
IH
Input High Voltage 3 V
I
IN
Input Current -5 +5 µA
V
O
Output Voltage SDA
Acknowledge
I
O
= 1.6mA 0.4 V
Table 5. Electrical Characteristics (continued)
Refer to the test circuit T
amb
= 25°C, V
S
= 9V, R
L
= 10KΩ, V
in
= 1Vrms; R
G
= 600Ω, all controls flat (G =
0dB), Effect Ctrl = -6dB, MODE = OFF; f = 1KHz unless otherwise specified.
Symbol Parameter Test Condition Min. Typ. Max. Unit
TDA7442 - TDA7442D
6/17
3I
2
C BUS INTERFACE
Data transmission from microprocessor to the TDA7442D and vice versa takes place through the 2 wires
I
2
C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage
must be connected).
3.1 Data Validity
As shown in fig. 5, the data on the SDA line must be stable during the high period of the clock. The HIGH
and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
3.2 Start and Stop Conditions
As shown in fig. 6 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The
stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
3.3 Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge
bit. The MSB is transferred first.
3.4 Acknowledge
The master (µP) puts a restive HIGH level on the SDA line during the acknowledge clock pulse (see fig.
3). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this
clock pulse.
The audio processor which has been addressed has to generate an acknowledge after the reception of
each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case
the master transmitter can generate the STOP information in order to abort the transfer.
3.5 Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio processor, the µP can use a simpler transmission: simply
it waits one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking.
Figure 5. Data Validity on the I
2
CBUS
Figure 6. Timing Diagram of I
2
CBUS
Figure 7. Acknowledge on the I
2
CBUS
S
DA
S
CL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
CL
DA
START
I
2
CBU
STOP
D99AU1032
S
CL
1
MSB
23789
S
DA
START
ACKNOWLEDGMEN
T
FROM RECEIVER
D99AU1033
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

TDA7442D013TR

Mfr. #:
Buy TDA7442D013TR
Manufacturer:
STMicroelectronics
Description:
Multimedia Misc Tone Control Suround Digtal Cntrold Audio
Lifecycle:
New from this manufacturer.
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