OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

CP2112-F02-GM

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
CP2112
Rev. 1.2 13
5. USB Function Controller and Transceiver
The Universal Serial Bus (USB) function controller in the CP2112 is a USB 2.0 compliant full-speed device with
integrated transceiver and on-chip matching and pullup resistors. The USB function controller manages all data
transfers between the USB and the SMBus interface as well as command requests generated by the USB host
controller and commands for controlling the function of the SMBus interface and GPIO pins.
The USB Suspend and Resume modes are supported for power management of both the CP2112 device and
external circuitry. The CP2112 enters Suspend mode when Suspend signaling is detected on the bus. Upon
entering Suspend mode, the Suspend signals are asserted. The Suspend signals are also asserted after a CP2112
reset until device configuration during USB enumeration is complete. SUSPEND is logic high when the device is in
the Suspend state and logic low when the device is in normal mode. The SUSPEND
pin has the opposite logic
value of the SUSPEND pin.
The CP2112 exits Suspend mode when any of the following events occur: Resume signaling is detected or
generated, a USB Reset signal is detected, or a device reset occurs. SUSPEND and SUSPEND
are weakly pulled
to VIO in a high-impedance state during a CP2112 reset. If this behavior is undesirable, a strong pulldown resistor
(10 k) can be used to ensure SUSPEND
remains low during reset. The eight GPIO pins will retain their state
during Suspend mode.
6. System Management Bus (SMBus) Interface
The SMBus I/O interface is a two-wire, bidirectional serial bus. The SMBus is compliant with the System
Management Bus Specification, Version 1.1, and compatible with the I
2
C serial bus. Reads and writes to the
interface by the system controller are byte-oriented with the SMBus interface autonomously controlling the serial
transfer of the data. The CP2112 operates as an SMBus master; however, it has an SMBus slave address that is
configurable. The CP2112 will only ACK this address and will not respond to any read or write requests. If the least
significant bit of the address is set, the device will ignore it.
6.1. SMBus Configuration
Figure 5 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage between
3.0 V and 5.0 V; different devices on the bus may operate at different voltage levels. The bidirectional serial clock
(SCL) and serial data (SDA) lines must be connected to a positive power supply voltage through a pullup resistor or
similar circuit. Every device connected to the bus must have an open-drain or open-collector output for both the
SCL and SDA lines so that both are pulled high (recessive state) when the bus is free. The maximum number of
devices on the bus is limited only by the requirement that the rise and fall times on the bus not exceed 300 ns and
1000 ns, respectively. The SMBus provides control of SDA, SCL generation and synchronization, arbitration logic,
and START/STOP control and generation.
Figure 5. Typical SMBus Configuration
VDD = 5 V
CP2112
(Master Device)
Slave
Device 1
Slave
Device 2
VDD = 3 V VDD = 5 V VDD = 3 V
SDA
SCL
CP2112
14 Rev. 1.2
6.2. SMBus Operation
The CP2112 supports reads, writes, and addressed reads. The master device initiates all three types of data
transfers and provides the clock pulses on SCL. The SMBus interface on the CP2112 operates as a master, but
also has a configurable slave address associated with it that the CP2112 will only ACK upon receiving. Multiple
master devices on the same bus are supported. If two or more masters attempt to initiate a data transfer
simultaneously, an arbitration scheme is employed with a single master always winning the arbitration. Note that it
is not necessary to specify one device as the Master in a system; any device that transmits a START and a slave
address becomes the master for the duration of that transfer.
A typical SMBus transaction consists of a START condition followed by an address byte (Bits7–1: 7-bit slave
address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Bytes that are received (by a
master or slave) are acknowledged (ACK) with a low SDA during a high SCL (see Figures 6, 7, and 8). If the
receiving device does not ACK, the transmitting device will read a NACK (not acknowledge), which is a high SDA
during a high SCL.
The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set to logic
1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation. All transactions are
initiated by a master, with one or more addressed slave devices as the target. The master generates the START
condition and then transmits the slave address and direction bit. If the transaction is a WRITE operation from the
master to the slave, the master transmits the data one byte at a time waiting for an ACK from the slave at the end
of each byte. For READ operations, the slave transmits the data waiting for an ACK from the master at the end of
each byte. At the end of the data transfer, the master generates a STOP condition to terminate the transaction and
free the bus. Figure 6 illustrates a typical CP2112 read transaction, and Figure 7 illustrates a typical CP2112 write
transaction.
Figure 6. Typical CP2112 Read
Figure 7. Typical CP2112 Write
The CP2112 performs addressed reads using a repeated start. Addressed Reads are implemented by issuing a
START condition followed by a slave address write and logical address. Next the CP2112 issues a repeated
START followed by a slave address read. After this sequence, the CP2112 reads bytes from the slave device. The
CP2112 supports addressed reads on slave devices with up to a 16 byte logical address field. Figure 8 illustrates a
typical addressed read transaction (with a one byte logical address field).
SLA6
SDA
SLA5-0 Write (0) D7 D6-0
SCL
Slave Address + Write Data ByteSTART ACK ACK STOP
CP2112
Rev. 1.2 15
Figure 8. Typical CP2112 Addressed Read
6.3. CP2112 Configuration Options
The CP2112 has the following SMBus configuration options, which are all configured through USB: clock speed,
device address, auto send read, read timeout, write timeout, SCL low timeout, and retry time.
The SMBus clock speed is configurable with a recommended operating range of 10 kHz to 400 kHz.
The device address is a configurable 7-bit address, which is the slave address of the CP2112. Although the
CP2112 is a master device, the CP2112 will ACK this address but will not respond to any read or write requests.
If the least significant bit is set, the CP2112 will ignore it.
If auto read send is set to 0x01, the CP2112 will return the results of a read automatically. If this is set to 0x00,
the device will wait for a “data read response” request to respond to data.
The read and write timeouts are the time limit before the device will automatically cancel a transfer that has
been initiated and can range from 0 to 1000 ms. If set to 0 ms, this indicates that there is no timeout.
The SCL low timeout is either enabled or disabled. If the SCL line is held low by a slave device on the bus, no
further communication is possible. Furthermore, the master cannot force the SCL line high to correct the error
condition. To solve this problem, the SMBus protocol specifies that devices participating in a transfer must
detect any clock cycle held low longer than 25 ms as a “timeout” condition. Devices that have detected the
timeout condition must reset the communication no later than 10 ms after detecting the timeout condition.
The retry time is the number of times the device will attempt a transfer before terminating the transfer. This can
be set from 0 to 1000. If set to 0, there is no retry limit.
These configuration options cannot be changed while a transfer is in progress.
Repeated
START
Read (1)
Slave Address + Read
SLA6-0
SDA
Write (0) ADDR7-0
SCL
Slave Address + Write Data ByteSTART ACK ACK
ACK
Logical
Address
SLA6-0
DATA7-0
NACK STOP
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

CP2112-F02-GM

Mfr. #:
Buy CP2112-F02-GM
Manufacturer:
Silicon Labs
Description:
USB Interface IC HID USB to SMBUS Bridge QFN24
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet