ATZB-256RFR2-XPRO

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ATmega256/128/64RFR2
3.2.22 CLKI
Input to the clock system. If selected, it provides the operating clock of the
microcontroller.
3.3 Unused Pins
Floating pins can cause power dissipation in the digital input stage. They should be
connected to an appropriate source. In normal operation modes the internal pull-up
resistors can be enabled (in Reset all GPIO are configured as input and the pull-up
resistors are still not enabled).
Bi-directional I/O pins shall not be connected to ground or power supply directly.
The digital input pins TST and CLKI must be connected. If unused pin TST can be
connected to AVSS while CLKI should be connected to DVSS.
Output pins are driven by the device and do not float. Power supply pins respective
ground supply pins are connected together internally.
XTAL1 and XTAL2 shall never be forced to supply voltage at the same time.
3.4 Configuration summary
According to the application requirements a variable memory size allows to optimize
current consumption and leakage current.
Table 3-1 Memory Configuration
Device Flash EEPROM SRAM
ATmega256RFR2 256KB 8KB 32KB
ATmega128RFR2 128KB 4KB 16KB
ATmega64RFR2 64KB 2KB 8KB
Package and associated pin configuration are the same for all devices providing full
functionality to the application.
Table 3-2 System Configuration
Device Package GPIO Serial IF ADC channel
ATmega256RFR2 QFN 38 2 USART, SPI, TWI 8
ATmega128RFR2 QFN 38 2 USART, SPI, TWI 8
ATmega64RFR2 QFN 38 2 USART, SPI, TWI 8
The devices are optimized for applications based on the ZigBee and the IEEE 802.15.4
specification. Having application stack, network layer, sensor interface and an excellent
power control combined in a single chip many years of operation should be possible.
Table 3-3 Application Profile
Device Application
ATmega256RFR2 Large Network Coordinator / Router for IEEE 802.15.4 / ZigBee Pro
ATmega128RFR2 Network Coordinator / Router for IEEE 802.15.4
ATmega64RFR2 End node device / network processor
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8393CS-MCU Wireless-09/14
ATmega256/128/64RFR2
3.5 Compatibility to ATmega1281/2561
The basic AVR feature set of the ATmega256/128/64RFR2 is derived from the
ATmega1281/2561. Address locations and names of the implemented modules and
registers are unchanged as long as it fits the target application of a very small and
power efficient radio system. In addition, several new features were added.
Backward compatibility of the ATmega256/128/64RFR2 to the ATmega1281/2561 is
provided in most cases. However some incompatibilities between the microcontrollers
exist.
3.5.1 Port A and Port C
Port A and Port C are not implemented. The associated registers are available but will
not provide any port control. Remaining ports are kept at their original address location
to not require changes of existing software packages.
3.5.2 External Memory Interface
The alternate pin function “External Memory interface” using Port A and Port C is not
implemented due to the missing ports.
The large internal data memory (SRAM) does not require an external memory and the
associated parallel interface. It keeps the system radiation (EMC) at a very small level
to provide very high sensitivity at the antenna input.
3.5.3 High Voltage Programming Mode
Alternate pin function BS2 (high voltage programming) of pin PA0 is mapped to a
different pin. Entering the parallel programming mode is controlled by the TST pin.
3.5.4 AVR Oscillators and External Clock
The AVR microcontroller can utilize the high performance crystal oscillator of the
2.4GHz transceiver connected to the pins XTAL1 and XTAL2. An external clock can be
applied to the microcontroller using the clock input CLKI.
3.5.5 Analog Frontend
The ATmega256/128/64RFR2 has a new A/D converter. Software compatibility is
basically assured. Nevertheless to benefit from the higher conversion speeds and the
better performance some changes are required.
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ATmega256/128/64RFR2
4 Application Circuits
4.1 Basic Application Schematic
A basic application schematic of the ATmega256/128/64RFR2 with a single-ended RF
connector is shown in Figure 4-1 below and the associated Bill of Material in Table 4-1
on page 10. The 50 single-ended RF input is transformed to the 100 differential RF
port impedance using Balun B1. The capacitors C1 and C2 provide AC coupling of the
RF input to the RF port, capacitor C4 improves matching.
Figure 4-1. Basic Application schematic (64-pin package)
8
7
6
5
4
3
2
1
17 18 19 20 21 22 23 24
5657585960616263
AREF
AVSS
AVSS
RFP
RFN
AVSS
TST
DVSS
DVDD
DVDD
XTAL2
DEVDD
DVSS
AVDD
EVDD
AVSS
XTAL1
41
42
43
44
45
46
47
48
PB0
DVSS
PE0
PB7
CB3
CB4
RSTN
V
DD
XTAL
CX1 CX2
CB1
V
DD
CB2
C1
C2
B1
RF
C4
25 26 27 28 29 30 31 32
16
14
13
12
11
10
9
15
64
5455 4950515253
33
34
35
36
37
38
39
40
RSTON
XTAL
32kHz
CX3 CX4
CLKI
DEVDD
DVSS
DEVDD
PE7
DVSS
DEVDD
PF0
PF7
PG0
PG5
PD0
PD7
Pins TST & CLKI
must be connected
The power supply bypass capacitors (CB2, CB4) are connected to the external analog
supply pin (EVDD, pin 59) and external digital supply pin (DEVDD, pin 23). Pins 34, 44
and 54 supply the digital port pins.
Floating pins can cause excessive power dissipation (e.g. during power on). They
should be connected to an appropriate source. GPIO shall not be connected to ground
or power supply directly.
The digital input pins TST and CLKI must be connected. If pin TST will never be used it
can be connected to AVSS while an unused pin CLKI could be connected to DVSS (see
chapter "Unused Pins" on page 7).
Capacitors CB1 and CB3 are bypass capacitors for the integrated analog and digital
voltage regulators to ensure stable operation and to improve noise immunity.

ATZB-256RFR2-XPRO

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
Daughter Cards & OEM Boards Xplained PRO Ext 256RFR2 ZigBit
Lifecycle:
New from this manufacturer.
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