9ZXL1230
12-OUTPUT LOW POWER DIFFERENTIAL BUFFER FOR PCIE GEN3 AND QPI
IDT®
12-OUTPUT LOW POWER DIFFERENTIAL BUFFER FOR PCIE GEN3 AND QPI 13
9ZXL1230 REV C 112015
SMBusTable: PLL Mode, and Frequency Select Re
ister
Pin # Name Control Function T
e 0 1 D efault
Bit 7
PLL Mode 1 PLL Operating Mode Rd ba ck 1
R
Bit 6
PLL Mode 0 PLL Operating Mode Rd ba ck 0
R
Latch
Bit 5
0
Bit 4
0
Bit 3
PLL_SW_EN Enable S/W control of PLL BW RW HW Latch SMBus Control 0
Bit 2
PLL Mode 1 PLL O
eratin
Mode 1 RW 1
Bit 1
PLL Mode 0 PLL O
eratin
Mode 1 RW 1
Bit 0
100M_133M# Frequency Select Readbac
R
133MHz 100MHz
Latch
SMBusTable: Output Control Re
iste
Pin # Name Control Function Type 0 1 Default
Bit 7
DIF_7_En Out
ut Control overrides OE#
in RW 1
Bit 6
DIF_6_En Out
ut Control overrides OE#
in RW 1
Bit 5
DIF_5_En Out
ut Control overrides OE#
in RW 1
Bit 4
DIF_4_En Output Control overrides OE# pin RW 1
Bit 3
DIF_3_En Output Control RW 1
Bit 2
DIF_2_En Out
ut Control RW 1
Bit 1
DIF_1_En Out
ut Control RW 1
Bit 0
DIF_0_En Out
ut Control RW 1
SMBusTable: Output Control Re
iste
Pin # Name Control Function Type 0 1 Default
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
Bit 3
DIF_11_En Out
ut Control RW 1
Bit 2
DIF_10_En Out
ut Control RW 1
Bit 1
DIF_9_En Output Control RW 1
Bit 0
DIF_8_En Out
ut Control RW 1
SMBusTable: Reserved Register
Pin # Name Control Function T
e 0 1 D efault
Bit 7
0
Bit 6
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
SMBusTable: Reserved Re
ister
Pin # Name Control Function Type 0 1 Default
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
SMBusTable: Vendor & Revision ID Re
iste
Pin # Name Control Function Type 0 1 Default
Bit 7
RID3 R
Bit 6
RID2 R
Bit 5
RID1 R
Bit 4
RID0 R
Bit 3
Bit 2
VID 2 R - - 0
Bit 1
VID 1 R - - 0
Bit 0
VID 0 R - - 1
Reserved
Reserved
Low/Low Enable
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Low/Low Enable
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
-
Byte 1
Byte 0
Byte 3
Byte 2
16/17
Byte 5
See PLL Operating Mode
Readback Table
REVISION ID
Reserved
Reserved
VEN DOR ID
See PLL Operating Mode
Readback Table
Note:
Setting bit 3 to '1' allows the user to overide the Latch value from pin 5 via use of bits 2 and 1. Use the values fro m the PLL Operating Mode
Readback Table. Note that Bits 7 and 6 will keep the value originally latche d on pin 5. A warm reset of the system will have to accomplished if the
user changes these bits.
Reserved
38/37
