9
LTC1655/LTC1655L
DEFI ITIO S
UU
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
DNL = (∆V
OUT
– LSB)/LSB
Where ∆V
OUT
is the measured voltage difference between
two adjacent codes.
Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
(nV)(sec).
Full-Scale Error (FSE): The deviation of the actual full-
scale voltage from ideal. FSE includes the effects of offset
and gain errors (see Applications Information).
Gain Error (GE): The difference between the full-scale
output of a DAC from its ideal full-scale value after offset
error has been adjusted.
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (Endpoint INL). Because the output cannot go below
zero, the linearity is measured between full scale and the
lowest code that guarantees the output will be greater than
zero. The INL error at a given input code is
calculated as
follows:
INL = [V
OUT
– V
OS
– (V
FS
– V
OS
)(code/65535)]/LSB
Where V
OUT
is the output voltage of the DAC measured at
the given input code.
Least Significant Bit (LSB): The ideal voltage difference
between two successive codes.
LSB = 2V
REF
/65536
Resolution (n): Defines the number of DAC output states
(2
n
) that divide the full-scale range. Resolution does not
imply linearity.
Voltage Offset Error (V
OS
): Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Applications Information).
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
OPERATIO
U
Serial Interface
The data on the D
IN
input is loaded into the shift register
on the rising edge of the clock. The MSB is loaded first. The
DAC register loads the data from the shift register when
CS/LD is pulled high. The clock is disabled internally when
CS/LD is high. Note: CLK must be low before CS/LD is
pulled low to avoid an extra internal clock pulse. The input
word must be 16 bits wide.
The buffered output of the 16-bit shift register is available
on the D
OUT
pin which swings from GND to V
CC
.
Multiple LTC1655s/LTC1655Ls may be daisy-chained to-
gether by connecting the D
OUT
pin to the D
IN
pin of the next
chip while the clock and CS/LD signals remain common to
all chips in the daisy chain. The serial data is clocked to all
of the chips, then the CS/LD signal is pulled high to update
all of them simultaneously. The shift register and DAC
register are cleared to all 0s on power-up.
Voltage Output
The LTC1655/LTC1655L rail-to-rail buffered output can
source or sink 5mA over the entire operating temperature
range while pulling to within 600mV of the positive supply
voltage or ground. The output stage is equipped with a
deglitcher that gives a midscale glitch of 12nV-s. At power-
up, the output clears to 0V.
The output swings to within a few millivolts of either sup-
ply rail when unloaded and has an equivalent output resis-
tance of 40Ω (70Ω for the LTC1655L) when driving a load
to the rails. The output can drive 1000pF without going into
oscillation.
