13
COMMERCIAL TEMPERATURE RANGE
IDT72V3623/72V3643 CMOS 3.3V SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36, 1,024 x 36
three cycles of the port Clock that reads data from the FIFO have not
elapsed since the time the word was written. The Output Ready flag of the
FIFO remains LOW until the third LOW-to-HIGH transition of the synchro-
nizing clock occurs, simultaneously forcing the Output Ready flag HIGH
and shifting the word to the FIFO output register.
In IDT Standard mode, from the time a word is written to a FIFO, the
Empty Flag will indicate the presence of data available for reading in a
minimum of two cycles of the Empty Flag synchronizing clock. Therefore,
an Empty Flag is LOW if a word in memory is the next data to be sent to
the FlFO output register and two cycles of the port Clock that reads data
from the FIFO have not elapsed since the time the word was written. The
Empty Flag of the FIFO remains LOW until the second LOW-to-HIGH
transition of the synchronizing clock occurs, forcing the Empty Flag HIGH;
only then can data be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag synchro-
nizing clock begins the first synchronization cycle of a write if the clock
transition occurs at time tSKEW1 or greater after the write. Otherwise, the
subsequent clock cycle can be the first synchronization cycle (see Figures
11 and 12).
FULL/INPUT READY FLAGS (FF/IR)
This is a dual purpose flag. In FWFT mode, the Input Ready (IR)
function is selected. In IDT Standard mode, the Full Flag (FF) function is
selected. For both timing modes, when the Full/Input Ready flag is HIGH,
a memory location is free in the FIFO to receive new data. No memory
locations are free when the Full/Input Ready flag is LOW and attempted
writes to the FIFO are ignored.
The Full/Input Ready flag of a FlFO is synchronized to the port clock that
writes data to its array (CLKA). For both FWFT and IDT Standard modes,
each time a word is written to a FIFO, its write pointer is incremented. The
state machine that controls a Full/Input Ready flag monitors a write pointer
and read pointer comparator that indicates when the FlFO memory status
is full, full-1, or full-2. From the time a word is read from a FIFO, its previous
memory location is ready to be written to in a minimum of two cycles of the
Full/Input Ready flag synchronizing clock. Therefore, an Full/Input Ready
flag is LOW if less than two cycles of the Full/Input Ready flag synchroniz-
ing clock have elapsed since the next memory write location has been
read. The second LOW-to-HIGH transition on the Full/Input Ready flag
synchronizing clock after the read sets the Full/Input Ready flag HIGH.
A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock
begins the first synchronization cycle of a read if the clock transition occurs at time
t
SKEW1 or greater after the read. Otherwise, the subsequent clock cycle
can be the first synchronization cycle (see Figures 13 and 14).
ALMOST-EMPTY FLAG (AE)
The Almost-Empty flag of a FIFO is synchronized to the port clock that reads
data from its array (CLKB). The state machine that controls an Almost-
Empty flag monitors a write pointer and read pointer comparator that
indicates when the FIFO memory status is almost-empty, almost-empty+1,
or almost-empty+2. The Almost-Empty state is defined by the contents of
register X. These registers are loaded with preset values during a FIFO
reset, programmed from Port A, or programmed serially (see Almost-
Empty flag and Almost-Full flag offset programming section). An Almost-
Empty flag is LOW when its FIFO contains X or less words and is HIGH
when its FIFO contains (X+1) or more words. Note that a data word present
in the FIFO output register has been read from memory.
Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing clock
are required after a FIFO write for its Almost-Empty flag to reflect the new level
of fill. Therefore, the Almost-Empty flag of a FIFO containing (X+1) or
more words remains LOW if two cycles of its synchronizing clock have
not elapsed since the write that filled the memory to the (X+1) level. An
Almost-Empty flag is set HIGH by the second LOW-to-HIGH transition of
its synchronizing clock after the FIFO write that fills memory to the (X+1)
level. A LOW-to-HIGH transition of an Almost-Empty flag synchronizing
clock begins the first synchronization cycle if it occurs at time tSKEW2 or
greater after the write that fills the FIFO to (X+1) words. Otherwise, the
subsequent synchronizing clock cycle may be the first synchronization
cycle. (See Figure 15).
ALMOST-FULL FLAG (AF)
The Almost-Full flag of a FIFO is synchronized to the port clock that
writes data to its array. The state machine that controls an Almost-Full flag
monitors a write pointer and read pointer comparator that indicates when
the FIFO memory status is almost-full, almost-full-1, or almost-full-2.
The Almost-Full state is defined by the contents of register Y. These
registers are loaded with preset values during a FlFO reset or, pro-
grammed from Port A, or programmed serially (see Almost-Empty flag
and Almost-Full flag offset programming section). An Almost-Full flag is
LOW when the number of words in its FIFO is greater than or equal to
(256-Y) or (1,024-Y) for the IDT72V3623 or IDT72V3643 respectively.
An Almost-Full flag is HIGH when the number of words in its FIFO is less
than or equal to [256-(Y+1)] or [1,024-(Y+1)] for the IDT72V3623 or
IDT72V3643 respectively. Note that a data word present in the FIFO
output register has been read from memory.
Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing
clock are required after a FIFO read for its Almost-Full flag to reflect the
new level of fill. Therefore, the Almost-Full flag of a FIFO containing [256/
1,024-(Y+1)] or less words remains LOW if two cycles of its synchroniz-
ing clock have not elapsed since the read that reduced the number of
words in memory to [256/1,024-(Y+1)]. An Almost-Full flag is set HIGH
by the second LOW-to-HIGH transition of its synchronizing clock after the
FIFO read that reduces the number of words in memory to
[256/1,024-(Y+1)]. A LOW-to-HIGH transition of an Almost-Full flag
synchronizing clock begins the first synchronization cycle if it occurs at
time tSKEW2 or greater after the read that reduces the number of words
in memory to [256/1,024-(Y+1)]. Otherwise, the subsequent synchro-
nizing clock cycle may be the first synchronization cycle (see Figure 16).
MAILBOX REGISTERS
Two 36-bit bypass registers are on the IDT72V3623/72V3643 to
pass command and control information between Port A and Port B
without putting it in queue. The Mailbox select (MBA, MBB) inputs choose
between a mail register and a FIFO for a port data transfer operation. The
usable width of both the Mail1 and Mail2 Registers matches the selected
bus size for Port B.
A LOW-to-HIGH transition on CLKA writes data to the Mail1 Register when
a Port A write is selected by CSA, W/RA, and ENA with MBA HIGH. If the
selected Port B bus size is 36 bits, the usable width of the Mail1 Register
employs data lines A0-A35. If the selected Port B bus size is 18 bits, then
the usable width of the Mail1 Register employs data lines A0-A17. (In this
case, A18-A35 are don’t care inputs.) If the selected Port B bus size is 9
bits, then the usable width of the Mail1 Register employs data lines A0-
A8. (In this case, A9-A35 are don’t care inputs.)
A LOW-to-HIGH transition on CLKB writes B0-B35 data to the Mail2
Register when a Port B write is selected by CSB, W/RB, and ENB with
MBB HIGH. If the selected Port B bus size is 36 bits, the usable width of
