NCV8141
http://onsemi.com
7
Using an emitter sense scheme, the amount of current
through the NPN pass transistor is monitored. Feedback
circuitry insures that the output current never exceeds a
preset limit.
Figure 8. Typical Circuit Waveforms for Output
Stage Protection
I
O
Load
Dump
V
IN
V
OUT
Thermal
Shutdown
Short
Circuit
> 30 V
Should the junction temperature of the power device
exceed 180°C (typ), the power transistor is turned off.
Thermal shutdown is an effective means to prevent die
overheating since the power transistor is the principle heat
source in the IC.
REGULATOR CONTROL FUNCTIONS
The NCV8141 differs from all other linear regulators in its
unique combination of control features.
Watchdog and ENABLE Function
V
OUT
is controlled by the logic functions ENABLE and
Watchdog (Table 1).
Table 1. V
OUT
as a Function of ENABLE and Watchdog
V
OUT
(V)
ENABLE
WDI
Slow Normal High Low
H 5 5 5 5
L 0 5 0 0
As long as ENABLE is high or ENABLE is low and the
Watchdog signal is normal, V
OUT
will be at 5.0 V (typ). If
ENABLE is low and the frequency of the Watchdog input
goes below the threshold frequency, the output transistor
turns off and the IC goes into SLEEP mode. Only the
ENABLE circuitry in the IC remains powered up, drawing
a quiescent current of less than 50 mA.
The Watchdog monitors the frequency of an incoming
WDI signal. If the signal falls below the WDI limit, a
frequency programmable pulse train is generated at the
RESET
lead (Figure 9) until the correct Watchdog input
signal reappears at the lead (ENABLE = HIGH).
The threshold limit of the watchdog function is set by the
value of C
DELAY
. The limit is determined according to the
following equation for the NCV8141:
t
WDI +
(1.3 10
5)
C
DELAY
or
The capacitor C
DELAY
also determines the frequency of
the RESET
signal and the POWER−ON−RESET (POR)
delay period.
RESET Function
The RESET function is activated when the Watchdog
frequency signal is below the watchdog threshold
(Figure 9), when the regulator is in its power up state
(Figure 10) or when V
OUT
drops below V
OUT
−4.5% for
more than 2.0 ms (Figure 11)
If the Watchdog signal falls outside of the preset voltage
or below the frequency threshold, a frequency
programmable pulse train is generated at the RESET
lead
(Figure 9) until the correct Watchdog input signal reappears
at the lead. The duration of the RESET
pulse is determined
by C
DELAY
according to the following equation:
t
WDI(RESET
)
+ (1.0 10
4)
C
DELAY
RESET
CIRCUIT WAVEFORMS WITH DELAYS
INDICATED
If an undervoltage condition exists, the voltage on the
RESET
lead goes low and the delay capacitor, C
DELAY
, is
discharged. RESET
remains low until output is in
regulation, the voltage on C
DELAY
exceeds the upper
threshold and the Watchdog input signal is valid (Figures 10
and 11). The delay after the output is in regulation is:
t
POR(typ)
+ (4.75 10
5)
C
DELAY
The RESET delay circuit is also programmed with the
external cap C
DELAY
.
The output of the reset circuit is an open collector NPN.
RESET
is operational down to V
OUT
= 1.0 V. Both RESET
and its delay are governed by comparators with hysteresis to
avoid undesirable oscillations.
