MAX5204–MAX5207
Low-Cost, Voltage-Output, 16-Bit DACs in µMAX
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DIGITAL INPUTS (DIN, SCLK, CS, CLR, LDAC)
Input High Voltage V
IH
2.1 V
Input Low Voltage V
IL
0.6 V
Input Hysteresis V
HYST
200
mV
Input Leakage I
IN
Digital inputs = 0 or V
DD
±1 µA
Input Capacitance C
IN
15 pF
POWER REQUIREMENTS
Positive Power Supply V
DD
2.7 3.6 V
Positive Supply Current I
DD
All digital inputs at 0 or V
DD
(Note 5) 0.5 1.5 mA
Shutdown Supply Current I
SHDN
All digital inputs at 0 or V
DD
110µA
TIMING CHARACTERISTICS
SCLK Frequency f
SCLK
10
100
ns
SCLK Pulse Width High t
CH
40 ns
SCLK Pulse Width Low t
CL
40 ns
DIN Setup Time t
DS
40 ns
DIN Hold Time t
DH
0ns
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
t
CSH
0ns
SCLK Rise to CS Fall Ignore t
CS0
10 ns
CS Rise to SCLK Rise Ignore t
CS1
40 ns
LDAC Pulse Width t
LDAC
40 ns
CS Rise to LDAC Low Setup t
LDACS
40 ns
SCLK Fall to CS Fall Ignore t
CSOL
10 ns
CS Pulse Width Low for Shutdown
t
CSWL
40 ns
CS Pulse Width High t
CSWH
100
Note 1: Static performance tested at V
DD
= +5.0V (MAX5204/MAX5205) and at V
DD
= +3.0V (MAX5206/MAX5207).
Note 2: INL and DNL are guaranteed for outputs between 0.5V to (V
DD
- 0.5V).
Note 3: Guaranteed monotonic.
Note 4: V
REF
= 4.096V (MAX5204/MAX5205) and V
REF
= 2.048V (MAX5206/MAX5207).
Note 5: R
L
= ∞, digital inputs are at V
DD
or DGND.
ELECTRICAL CHARACTERISTICS—MAX5206/MAX5207 (continued)
(V
DD
= +2.7V to +3.6V, f
SCLK
= 10MHz (50% duty cycle), V
REF
= 2.048V, output load = 10kΩ in parallel with 250pF, T
A
= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.)
