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SI6924AEDQ-T1-E3

P1-P3P4-P6P7-P7
Vishay Siliconix
Si6924AEDQ
Document Number: 72215
S-81056-Rev. B, 12-May-08
www.vishay.com
1
N-Channel 2.5-V (G-S) Battery Switch, ESD Protection
FEATURES
• Halogen-free
• Low R
DS(on)
•V
GS
Max Rating: 14 V
• Exceeds 2 kV ESD Protection
• 28 V V
DS
Rated
• Symmetrical Voltage Blocking (Off Voltage)
PRODUCT SUMMARY
V
DS
(V) R
DS(on)
(Ω)I
D
(A)
28
0.033 at V
GS
= 4.5 V
4.6
0.038 at V
GS
= 3.0 V
4.3
0.042 at V
GS
= 2.5 V
4.1
DESCRIPTION
The Si6924AEDQ is a dual N-Channel MOSFET with ESD
protection and gate over-voltage protection circuitry
incorporated into the MOSFET. The device is designed for
use in Lithium Ion battery pack circuits. The common-drain
construction takes advantage of the typical battery pack
topology, allowing a further reduction of the device’s on-
resistance. The 2-stage input protection circuit is a unique
design, consisting of two stages of back-to-back zener
diodes separated by a resistor. The first stage diode is
designed to absorb most of the ESD energy. The second
stage diode is designed to protect the gate from any
remaining ESD energy and over-voltages above the gates
inherent safe operating range. The series resistor used to
limit the current through the second stage diode during over
voltage conditions has a maximum value which limits the
input current to ≤ 10 mA at 14 V and the maximum t
off
to 12
µs. The Si6924AEDQ has been optimized as a battery or
load switch in Lithium Ion applications with the advantage of
both a 2.5 V R
DS(on)
rating and a safe 14 V gate-to-source
maximum rating.
APPLICATION CIRCUITS
Figure 1. Typical Use In a Lithium Ion Battery Pack
Battery Protection Circuit
ESD and
Overvoltage
Protection
ESD and
Overvoltage
Protection
*Thermal connection to drain
p
ins is re
q
uired to achieve s
p
ecific
p
erformance
Figure 2. Input ESD and Overvoltage Protection Circuit
G
R**
S
D
**R typical value is 3.3 kΩ by design.
See Typical Characteristics,
Gate-Current vs. Gate-Source Voltage, Page 3.
RoHS
COMPLIANT
www.vishay.com
2
Document Number: 72215
S-81056-Rev. B, 12-May-08
Vishay Siliconix
Si6924AEDQ
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
Notes:
a. Surface Mounted on FR4 board.
Figure 3.
Ordering Information: Si6924AEDQ-T1-GE3 (Lead (Pb)-free and Halogen-free)
Si6924AEDQ
D
S
1
S
1
G
1
1
2
3
4
8
7
6
5
D
S
2
S
2
G
2
TSSOP-8
Top View
Figure 4.
G
1
S
1
G
2
S
2
N-Channel N-Channel
3.3 kΩ
3.3 kΩ
*D *D
*Thermal connection to drain pins is required to achieve specific performance
.
ABSOLUTE MAXIMUM RATINGS T
A
= 25 °C, unless otherwise noted
Parameter Symbol 10 s Steady State Unit
Drain-Source Voltage, Source-Drain Voltage
V
DS
28
V
Gate-Source Voltage
V
GS
± 14
Continuous Drain-to-Source Current (T
J
= 150 °C)
a
T
A
= 25 °C
I
D
4.6 4.1
A
T
A
= 70 °C
3.7 3.2
Pulsed Drain-to-Source Current
I
DM
20
Pulsed Source Current (Diode Conduction)
a
I
S
1.2 0.9
Maximum Power Dissipation
a
T
A
= 25 °C
P
D
1.3 1.0
W
T
A
= 70 °C
0.84 0.64
Operating Junction and Storage Temperature Range
T
J
, T
stg
- 55 to 150 °C
THERMAL RESISTANCE RATINGS
Parameter Symbol Typical Maximum Unit
Maximum Junction-to-Ambient
a
t ≤ 10 s
R
thJA
71 95
°C/W
Steady State 96 125
Maximum Junction-to-Foot (Drain) Steady State
R
thJF
56 70
Document Number: 72215
S-81056-Rev. B, 12-May-08
www.vishay.com
3
Vishay Siliconix
Si6924AEDQ
Notes:
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
SPECIFICATIONS T
J
= 25 °C, unless otherwise noted
Parameter Symbol Test Conditions Min. Typ. Max. Unit
Static
Gate Threshold Voltage
V
GS(th)
V
DS
= V
GS
, I
D
= 250 µA
0.6 1.5 V
Gate-Body Leakage
I
GSS
V
DS
= 0 V, V
GS
= ± 4.5 V
± 1 µA
V
DS
= 0 V, V
GS
= ± 14 V
± 20 mA
Zero Gate Voltage Drain Current
I
DSS
V
DS
= 22.4 V, V
GS
= 0 V
1
µA
V
DS
= 22.4 V, V
GS
= 0 V, T
J
= 55 °C
5
On-State Drain Current
b
I
D(on)
V
DS
≥ 5 V, V
GS
= 5 V
10 A
Drain-Source On-State Resistance
b
R
DS(on)
V
GS
= 4.5 V, I
D
= 4.6 A
0.022 0.033
Ω
V
GS
= 3.0 V, I
D
= 4.3 A
0.025 0.038
V
GS
= 2.5 V, I
D
= 4.1 A
0.029 0.042
Forward Transconductance
b
g
fs
V
DS
= 10 V, I
D
= 4.6 A
25 S
Diode Forward Voltage
b
V
SD
I
S
= 1.2 A, V
GS
= 0 V
0.7 1.1 V
Dynamic
a
Total Gate Charge
Q
g
V
DS
= 10 V, V
GS
= 4.5 V, I
D
= 4.6 A
6.5 10
nCGate-Source Charge
Q
gs
1.2
Gate-Drain Charge
Q
gd
1.5
Tu r n - On D e l ay T i m e
t
d(on)
V
DD
= 10 V, R
L
= 10 Ω
I
D
≅ 1 A, V
GEN
= 4.5 V, R
G
= 6 Ω
0.95 1.5
µs
Rise Time
t
r
1.4 2.1
Turn-Off Delay Time
t
d(off)
711
Fall Time
t
f
3.1 5
Gate-Current vs. Gate-Source Voltage
0.000
0.005
0.010
0.015
0.020
0 3 6 9 12 15
- Gate Current (mA)I
GSS
V
GS
- Gate-to-Source Voltage (V)
Gate Current vs. Gate-Source Voltage
14
0.001
100
10,000
04
T
J
= 25 °C
- Gate Current (A)I
GSS
0.01
0.1
1
10
1,000
V
GS
- Gate-to-Source Voltage (V)
T
J
= 150 °C
2681012
P1-P3P4-P6P7-P7

SI6924AEDQ-T1-E3

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Buy SI6924AEDQ-T1-E3
Manufacturer:
Vishay
Description:
MOSFET 2N-CH 28V 4.1A 8-TSSOP
Lifecycle:
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