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MC74HC4046AFELG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
© Semiconductor Components Industries, LLC, 2005
June, 2005 − Rev. 8
1 Publication Order Number:
MC74HC4046A/D
MC74HC4046A
Phase−Locked Loop
High−Performance Silicon−Gate CMOS
The MC74HC4046A is similar in function to the MC14046 Metal
gate CMOS device. The device inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with
LSTTL outputs.
The HC4046A phase−locked loop contains three phase
comparators, a voltage−controlled oscillator (VCO) and unity gain
op−amp DEM
OUT
. The comparators have two common signal inputs,
COMP
IN
, and SIG
IN
. Input SIG
IN
and COMP
IN
can be used directly
coupled to large voltage signals, or indirectly coupled (with a series
capacitor to small voltage signals). The self−bias circuit adjusts small
voltage signals in the linear region of the amplifier. Phase comparator
1 (an exclusive OR gate) provides a digital error signal PC1
OUT
and
maintains 90 degrees phase shift at the center frequency between
SIG
IN
and COMP
IN
signals (both at 50% duty cycle). Phase
comparator 2 (with leading−edge sensing logic) provides digital error
signals PC2
OUT
and PCP
OUT
and maintains a 0 degree phase shift
between SIG
IN
and COMP
IN
signals (duty cycle is immaterial). The
linear VCO produces an output signal VCO
OUT
whose frequency is
determined by the voltage of input VCO
IN
signal and the capacitor
and resistors connected to pins C1A, C1B, R1 and R2. The unity gain
op−amp output DEM
OUT
with an external resistor is used where the
VCO
IN
signal is needed but no loading can be tolerated. The inhibit
input, when high, disables the VCO and all op−amps to minimize
standby power consumption.
Applications include FM and FSK modulation and demodulation,
frequency synthesis and multiplication, frequency discrimination,
tone decoding, data synchronization and conditioning,
voltage−to−frequency conversion and motor speed control.
Features
• Output Drive Capability: 10 LSTTL Loads
• Low Power Consumption Characteristic of CMOS Devices
• Operating Speeds Similar to LSTTL
• Wide Operating Voltage Range: 3.0 to 6.0 V
• Low Input Current: 1.0 mA Maximum (except SIG
IN
and COMP
IN
)
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Low Quiescent Current: 80 mA Maximum (VCO disabled)
• High Noise Immunity Characteristic of CMOS Devices
• Diode Protection on all Inputs
• Chip Complexity: 279 FETs or 70 Equivalent Gates
• Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
MARKING
DIAGRAMS
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
1
16
PDIP−16
N SUFFIX
CASE 648
1
16
1
16
1
16
MC74HC4046AN
AWLYYWWG
1
16
HC4046AG
AWLYWW
HC40
46A
ALYWG
G
1
16
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G = Pb−Free Package
G = Pb−Free Package
(Note: Microdot may be in either location)
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
1
16
74HC4046A
ALYWG
SOEIAJ−16
F SUFFIX
CASE 966
1
16
MC74HC4046A
http://onsemi.com
2
Pin No. Symbol Name and Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PCP
OUT
PC1
OUT
COMP
IN
VCO
OUT
INH
C1A
C1B
GND
VCO
IN
DEM
OUT
R1
R2
PC2
OUT
SIG
IN
PC3
OUT
V
CC
Phase Comparator Pulse Output
Phase Comparator 1 Output
Comparator Input
VCO Output
Inhibit Input
Capacitor C1 Connection A
Capacitor C1 Connection B
Ground (0 V) V
SS
VCO Input
Demodulator Output
Resistor R1 Connection
Resistor R2 Connection
Phase Comparator 2 Output
Signal Input
Phase Comparator 3 Output
Positive Supply Voltage
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V
V
in
DC Input Voltage (Referenced to GND) – 1.5 to V
CC
+ 1.5 V
V
out
DC Output Voltage (Referenced to GND) – 0.5 to V
CC
+ 0.5 V
I
in
DC Input Current, per Pin ± 20 mA
I
out
DC Output Current, per Pin ± 25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ± 50 mA
P
D
Power Dissipation in Still Air Plastic DIP†
SOIC Package†
750
500
mW
T
stg
Storage Temperature – 65 to + 150
_C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP and SOIC Package†
260
_C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are not
valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 3.0 6.0 V
V
CC
DC Supply Voltage (Referenced to GND) NON−VCO 2.0 6.0 V
V
in
, V
out
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
CC
V
T
A
Operating Temperature, All Package Types – 55 + 125
_C
t
r
, t
f
Input Rise and Fall Time V
CC
= 2.0 V
(Pin 5) V
CC
= 4.5 V
V
CC
= 6.0 V
0
0
0
1000
500
400
ns
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
Figure 1. Pin Assignment
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
R2
PC2
out
SIG
in
PC3
out
V
CC
VCO
in
DEM
out
R1
VCO
out
COMP
in
PC1
out
PCP
out
GND
C1B
C1A
INH
MC74HC4046A
http://onsemi.com
3
[Phase Comparator Section]
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbo
l
Parameter Test Conditions
V
CC
V
Guaranteed Limit
Unit
– 55 to
25_C
≤ 85°C
≤ 125°C
V
IH
Minimum High−Level Input
Voltage DC Coupled
SIG
IN
, COMP
IN
V
out
= 0.1 V or V
CC
− 0.1 V
|I
out
| ≤ 20 mA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
IL
Maximum Low−Level Input
Voltage DC Coupled
SIG
IN
, COMP
IN
V
out
= 0.1 V or V
CC
− 0.1 V
|I
out
| ≤ 20 mA
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
OH
Minimum High−Level
Output Voltage
PCP
OUT
, PCn
OUT
V
in
= V
IH
or V
IL
|I
out
| ≤ 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
in
= V
IH
or V
IL
|I
out
| ≤ 4.0 mA
|I
out
| ≤ 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
V
OL
Maximum Low−Level
Output Voltage Qa−Qh
PCP
OUT
, PCn
OUT
V
out
= 0.1 V or V
CC
− 0.1 V
|I
out
| ≤ 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
|I
out
| ≤ 4.0 mA
|I
out
| ≤ 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
I
in
Maximum Input Leakage Current
SIG
IN
, COMP
IN
V
in
= V
CC
or GND 2.0
3.0
4.5
6.0
± 3.0
± 7.0
± 18.0
± 30.0
± 4.0
± 9.0
± 23.0
± 38.0
± 5.0
± 11.0
± 27.0
± 45.0
mA
I
OZ
Maximum Three−State
Leakage Current
PC2
OUT
Output in High−Impedance State
V
in
= V
IH
or V
IL
V
out
= V
CC
or GND
6.0 ± 0.5 ± 5.0 ± 10
mA
I
CC
Maximum Quiescent Supply Current
(per Package) (VCO disabled)
Pins 3, 5 and 14 at V
CC
Pin 9 at GND; Input Leakage at
Pins 3 and 14 to be excluded
V
in
= V
CC
or GND
|I
out
| = 0 mA
6.0 4.0 40 160
mA
NOTE:Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book
(DL129/D).
[Phase Comparator Section]
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Symbo
l
Parameter
V
CC
V
Guaranteed Limit
Unit
– 55 to
25_C
≤ 85°C ≤ 125°C
t
PLH
,
t
PHL
Maximum Propagation Delay, SIG
IN
/COMP
IN
to PC1
OUT
(Figure 2)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, SIG
IN
/COMP
IN
to PCP
OUT
(Figure 2)
2.0
4.5
6.0
340
68
58
425
85
72
510
102
87
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, SIG
IN
/COMP
IN
to PC3
OUT
(Figure 2)
2.0
4.5
6.0
270
54
46
340
68
58
405
81
69
ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, SIG
IN
/COMP
IN
Output
Disable Time to PC2
OUT
(Figures 3 and 4)
2.0
4.5
6.0
200
40
34
250
50
43
300
60
51
ns
t
PZH
,
t
PZL
Maximum Propagation Delay, SIG
IN
/COMP
IN
Output
Enable Time to PC2
OUT
(Figures 3 and 4)
2.0
4.5
6.0
230
46
39
290
58
49
345
69
59
ns
t
TLH
,
t
THL
Maximum Output Transition Time
(Figure 2)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

MC74HC4046AFELG

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Buy MC74HC4046AFELG
Manufacturer:
ON Semiconductor
Description:
Phase Locked Loops - PLL LOG CMOS PLL
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