ISL29033IROZ-EVALZ

ISL29033
7
FN7656.5
September 28, 2016
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transaction begins with the master asserting a start condition
(SDA falling while SCL remains high). The following byte is driven
by the master and includes the slave address and the read/write
bit. The receiving device is responsible for pulling SDA low during
the acknowledgment period. Every I
2
C transaction ends with the
master asserting a stop condition (SDA rising while SCL remains
high).
For more information about the I
2
C standard, consult the
Philips
I
2
C specification documents.
FIGURE 2. I
2
C TIMING DIAGRAM
FIGURE 3. I
2
C READ TIMING DIAGRAM SAMPLE
START
W
A A
A6 A5 A4 A3 A2 A1 A0 W
A R7 R6 R5 R4 R3 R2 R1 R0 A A6 A5 A4 A3 A2 A1 A0 W A
A A AD7D6D5D4D3D2D1D0
1357
1357
123456 9 2 4 6
STOP START
SDA DRIVEN BY MASTER
DEVICE ADDRESS
SDA DRIVEN BY ISL29033
DATA BYTE0REGISTER ADDRESS
OUT
DEVICE ADDRESSI
2
C DATA
SDA DRIVEN BY MASTERSDA DRIVEN BY MASTER
2468
924689
78135789
I
2
C SDA
I
2
C SDA
I
2
C CLK
IN
ISL29033
8
FN7656.5
September 28, 2016
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Register Set
There are eight registers available in the ISL29033. Table 1
summarizes their functions.
Command Register I 00 (Hex)
The first command register has the following functions:
1. Operation Mode: Bits 7, 6 and 5. These three bits determine
the operation mode of the device (Table 2
).
2. Interrupt flag: Bit 2. This is the status bit of the interrupt
(Table 3). The bit is set to logic high when the interrupt
thresholds have been triggered (out of threshold window) and
to logic low when not yet triggered. When activated and the
interrupt is triggered, the INT
pin goes low and the interrupt
status bit goes high until the status bit is polled through the
I
2
C read command. Both the INT output and the interrupt
status bit are automatically cleared at the end of the 8-bit
(00h) command register transfer.
3. Interrupt Persist: Bits 1 and 0. The interrupt pin and the
interrupt flag are triggered or set when the data sensor
reading is out of the interrupt threshold window after m
consecutive number of integration cycles (Table 4 on page 9
).
The interrupt persist bits determine m.
FIGURE 4. I
2
C WRITE TIMING DIAGRAM SAMPLE
START W A A
A6 A5 A4 A3 A2 A1 A0 W
A R7 R6 R5 R4 R3 R2 R1 R0 A B7 B6 B5 B4 B3 B2 B1 B0 A
A
12615948
STOP
SDA DRIVEN BY MASTER
FUNCTIONSREGISTER ADDRESSDEVICE ADDRESS
SDA DRIVEN BY MASTER
SDA DRIVEN BY MASTER
I
2
C DATA
I
2
C SDA IN
I
2
C SDA OUT
I
2
C CLK IN
AA
345 789 234 678 123 567 9
A
TABLE 1. REGISTER SET
ADDR REG NAME
BIT
765 4 3210DEFAULT
00h COMMANDI OP2 OP1 OP0 0 0 FLAG PRST1 PRST0 00h
01h COMMANDII 0 0 0 0 RES1 RES0 RANGE 1 RANGE 0 00h
02h DATA
LSB
D7 D6 D5 D4 D3 D2 D1 D0 00h
03h DATA
MSB
D15 D14 D13 D12 D11 D10 D9 D8 00h
04h INT_LT_LSB TL7 TL6 TL5 TL4 TL3 TL2 TL1 TL0 00h
05h INT_LT_MSB TL15 TL14 TL13 TL12 TL11 TL10 TL9 TL8 00h
06h INT_HT_LSB TH7 TH6 TH5 TH4 TH3 TH2 TH1 TH0 FFh
07h INT_HT_MSB TH15 TH14 TH13 TH12 TH11 TH10 TH9 TH8 FFh
TABLE 2. OPERATION MODE
BITS 7 TO 5 OPERATION
000 Power-down the device
001 Reserved (do not use)
010 Reserved (do not use)
100 Reserved (do not use)
101 ALS continuous
110 IR continuous
111 Reserved (do not use)
TABLE 3. INTERRUPT FLAG
BIT 2 OPERATION
0 Interrupt is cleared or not triggered yet
1 Interrupt is triggered
ISL29033
9
FN7656.5
September 28, 2016
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Command Register II 01 (Hex)
The second command register has the following functions:
1. Resolution: Bits 3 and 2. Bits 3 and 2 determine the ADC
resolution and the number of clock cycles per conversion
(Table 5
). Changing the number of clock cycles does more than
just change the resolution of the device; it also changes the
integration time, which is the period during which the
Analog-to-Digital (A/D) converter samples the photodiode
current signal for a measurement.
2. Range: Bits 1 and 0. The Full Scale Range (FSR) can be
adjusted through the I
2
C by using Bits 1 and 0. Table 6 lists
the possible values of FSR for the 499kΩ R
EXT
resistor.
Data Registers (02 Hex and 03 Hex)
The device has two 8-bit read-only registers to hold the data from
LSB to MSB for the ADC (Table 7
). The Most Significant Bit (MSB)
is accessed at 03 hex and the Least Significant Bit (LSB) is
accessed at 02 hex. For 16-bit resolution, the data is from D0 to
D15; for 12-bit resolution, the data is from D0 to D11; for 8-bit
resolution, the data is from D0 to D7. The registers are refreshed
after every conversion cycle.
Interrupt Registers (04, 05, 06, and 07 Hex)
Registers 04 and 05 hex set the Low (LO) threshold for the
interrupt pin and the interrupt flag. Register 04 hex is the LSB
and Register 05 hex is the MSB. By default, the interrupt
threshold LO is 00 hex for both LSB and MSB.
Registers 06 and 07 hex set the High (HI) threshold for the
interrupt pin and the interrupt flag. Register 06 hex is the LSB
and Register 07 hex is the MSB. By default, the interrupt
threshold HI is FF hex for both LSB and MSB.
Calculating Lux
The ISL29033 ADC output codes, DATA, are directly proportional
to lux in ambient light sensing, as shown in Equation 1.
In this equation, E
cal
is the calculated lux reading. The constant,
α, is determined by the full scale range and the ADC maximum
output counts. The constant is independent of the light sources
(fluorescent, incandescent, and sunlight) because the light
source IR component is removed during the light signal process.
The constant can also be viewed as the sensitivity (the smallest
lux measurement the device can measure), as shown in
Equation 2
.
In this equation, Range(k) is as defined in Table 6
. Count
max
is
the maximum output counts from the ADC.
The transfer function used for n-bits ADC is as shown in
Equation 3
:
In this equation, n = 4, 8, 12 or 16 and is the number of ADC bits
programmed in the command register. The number 2
n
represents the maximum number of counts possible from the
ADC output. Data is the ADC output stored in data
Registers 02 hex and 03 hex.
Integration and Conversion Time
ADC resolution and f
OSC
determine the integration time, t
int
, as
shown in Equation 4
.
In this equation, n is the number of bits of resolution and n = 4, 8,
12 or 16. Therefore, 2
n
is the number of clock cycles. The value
of n can be programmed at the command register, Register 01
hex, Bits 3 and 2 see (Table 8
).
TABLE 4. INTERRUPT PERSIST
BIT 1:0 NUMBER OF INTEGRATION CYCLES
00 1
01 4
10 8
11 16
TABLE 5. ADC RESOLUTION DATA WIDTH
BITS 3:2 NUMBER OF CLOCK CYCLES n-BIT ADC
00 2
16
= 65,536 16
01 2
12
= 4,096 12
10 2
8
= 256 8
11 2
4
= 16 4
TABLE 6. RANGE/FSR LUX
BITS 1:0 k RANGE(k) FSR (lux) AT ALS SENSING
00 1 Range1 125
01 2 Range2 500
10 3 Range3 2,000
11 4 Range4 8,000
TABLE 7. DATA REGISTERS
ADDRESS
(HEX) CONTENTS
02 D0 is LSB for 4-, 8-, 12- or 16-bit resolution; D3 is MSB for
4-bit resolution; D7 is MSB for 8-bit resolution
03 D15 is MSB for 16-bit resolution; D11 is MSB for 12-bit
resolution
TABLE 8. INTEGRATION TIME OF n-BIT ADC
R
EXT
(kΩ)
n = 16-BIT
(ms)
n = 12-BIT
(ms)
n = 8-BIT
(µs)
n = 4-BIT
(µs)
499 100 6.25 391 24
1000 200 12.5 782 48
E
cal
DATA=
(EQ. 1)
Range k
Count
max
----------------------------
=
(EQ. 2)
(EQ. 3)
E
cal
Range k
2
n
---------------------------
DATA=
t
int
2
n
1
f
OSC
--------------
2
n
R
EXT
655kHz 499k
----------------------------------------------
==
(EQ. 4)

ISL29033IROZ-EVALZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Optical Sensor Development Tools ISL29033IROZ-EVALZ (PB-Free ) EVALUATION BOARD - ROHs Compli
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