74AHC_AHCT373_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 20 May 2008 9 of 17
NXP Semiconductors
74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state
[1] Typical values are measured at nominal supply voltage (V
CC
= 3.3 V and V
CC
= 5.0 V).
[2] t
pd
is the same as t
PHL
and t
PLH
.
[3] t
en
is the same as t
PZH
and t
PZL
.
[4] t
dis
is the same as t
PHZ
and t
PLZ
.
[5] C
PD
is used to determine the dynamic power dissipation (P
D
in µW).
P
D
=C
PD
× V
CC
2
× f
i
× N+Σ(C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
Σ(C
L
× V
CC
2
× f
o
) = sum of the outputs.
t
h
hold time Dn to LE; see Figure 10
V
CC
= 3.0 V to 3.6 V 1.0 - - 1.0 - 1.0 - ns
V
CC
= 4.5 V to 5.5 V 1.0 - - 1.0 - 1.0 - ns
C
PD
power
dissipation
capacitance
f
i
= 1 MHz;
V
I
= GND to V
CC
[5]
-10- - - - -pF
74AHCT373; V
CC
= 4.5 V to 5.5 V
t
pd
propagation
delay
Dn to Qn; see Figure 7
[4]
C
L
= 15 pF - 4.0 8.5 1.0 9.5 1.0 11.0 ns
C
L
= 50 pF - 5.2 9.5 1.0 10.5 1.0 12.0 ns
LE to Qn; see
Figure 8
C
L
=15pF
[4]
- 4.3 12.3 1.0 13.5 1.0 15.5 ns
C
L
= 50 pF - 5.5 13.3 1.0 14.5 1.0 17.0 ns
t
en
enable time OE to Qn; see Figure 9
C
L
= 15 pF - 4.0 10.9 1.0 12.5 1.0 14.0 ns
C
L
=50pF
[4]
- 5.2 11.9 1.0 13.5 1.0 15.0 ns
t
dis
disable time OE to Qn; see Figure 9
C
L
= 15 pF - 4.4 10.2 1.0 11.0 1.0 13.0 ns
C
L
= 50 pF - 6.5 11.2 1.0 12.0 1.0 14.0 ns
t
W
pulse width LE HIGH; see Figure 8
[4]
6.5 - - 6.5 - 6.5 - ns
t
su
set-up time Dn to LE; see Figure 10 3.5 - - 3.5 - 3.5 - ns
t
h
hold time Dn to LE; see Figure 10 1.5 - - 1.5 - 1.5 - ns
C
PD
power
dissipation
capacitance
f
i
= 1 MHz;
V
I
= GND to V
CC
[5]
-12- - - - -pF
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.
Symbol Parameter Conditions 25 °C −40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ
[1]
Max Min Max Min Max
