7
2007 Semtech Corp.
www.semtech.com
POWER MANAGEMENT
SC1189
Careful attention to layout requirements are necessary for
successful implementation of the SC1189 PWM control-
ler. High currents switching at 200kHz are present in the
application and their effect on ground plane voltage differ-
entials must be understood and minimized.
1). The high power parts of the circuit should be laid out
first. A ground plane should be used, the number and
position of ground plane interruptions should be such as
to not unnecessarily compromise ground plane integrity.
Isolated or semi-isolated areas of the ground plane may
be deliberately introduced to constrain ground currents to
particular areas, for example the input capacitor and bot-
tom FET ground.
2). The loop formed by the Input Capacitor(s) (Cin), the Top
FET (Q1) and the Bottom FET (Q2) must be kept as small
as possible. This loop contains all the high current, fast
Layout Guidelines
transition switching. Connections should be as wide and
as short as possible to minimize loop inductance. Mini-
mizing this loop area will a) reduce EMI, b) lower ground
injection currents, resulting in electrically “cleaner” grounds
for the rest of the system and c) minimize source ringing,
resulting in more reliable gate switching signals.
3). The connection between the junction of Q1, Q2 and
the output inductor should be a wide trace or copper re-
gion. It should be as short as practical. Since this connec-
tion has fast voltage transitions, keeping this connection
short will minimize EMI. The connection between the out-
put inductor and the sense resistor should be a wide trace
or copper area, there are no fast voltage or current transi-
tions in this connection and length is not so important,
however adding unnecessary impedance will reduce effi-
ciency.
Vout
12V IN
3.3V Vo Lin1
Vo Lin2
5V
L
5mOhm
+
Cout
+
Cin
10
Q2
0.1uF
Q3
+
Cout Lin1
2.32k
Q4
+
Cout Lin2
1.00k
+
Cin Lin
SC1189
AGND
1
VCC
5
PWRGD
6
LDOEN
7
CS-
8
CS+
9
PGNDH
10
DH
11
BSTH
15
EN
16
VOSENSE
17
VID25MV
18
VID3
19
VID2
20
VID1
21
VID0
22
DL
13
PGNDL
12
BSTL
14
GATE2
24
GATE1
2
LDOV
23
LDOS1
3
LDOS2
4 Q1
0.1uF
Heavy lines indicate
high current paths.
Layout Diagram
SC1189
82007 Semtech Corp.
www.semtech.com
POWER MANAGEMENT
SC1189
Layout Guidelines (Cont.)
4) The Output Capacitor(s) (Cout) should be located as
close to the load as possible, fast transient load currents
are supplied by Cout only, and connections between Cout
and the load must be short, wide copper areas to mini-
mize inductance and resistance.
5) The SC1189 is best placed over a quiet ground plane
area, avoid pulse currents in the Cin, Q1, Q2 loop flowing
in this area. PGNDH and PGNDL should be returned to
the ground plane close to the package. The AGND pin
should be connected to the ground side of (one of) the
output capacitor(s). If this is not possible, the AGND pin
may be connected to the ground path between the Output
Capacitor(s) and the Cin, Q1, Q2 loop. Under no circum-
stances should AGND be returned to a ground inside the
Cin, Q1, Q2 loop.
6) Vcc for the SC1189 should be supplied from the 5V
supply through a 10 resistor, the Vcc pin should be
decoupled directly to AGND by a 0.1µF ceramic capacitor,
trace lengths should be as short as possible.
7) The Current Sense resistor and the divider across it
should form as small a loop as possible, the traces run-
ning back to CS+ and CS- on the SC1189 should run par-
allel and close to each other. The 0.1µF capacitor should
be mounted as close to the CS+ and CS- pins as possible.
8) Ideally, the grounds for the two LDO sections should be
returned to the ground side of (one of) the output
capacitor(s).
Vout
5V
+
+
Currents in Power Section
9
2007 Semtech Corp.
www.semtech.com
POWER MANAGEMENT
SC1189
Component Selection
SS
SS
S
WITWIT
WITWIT
WIT
CHING SECTIONCHING SECTION
CHING SECTIONCHING SECTION
CHING SECTION
OUTPUT CAPOUTPUT CAP
OUTPUT CAPOUTPUT CAP
OUTPUT CAP
AA
AA
A
CITCIT
CITCIT
CIT
ORSORS
ORSORS
ORS - Selection begins with the most
critical component. Because of fast transient load current
requirements in modern microprocessor core supplies, the
output capacitors must supply all transient load current
requirements until the current in the output inductor ramps
up to the new level. Output capacitor ESR is therefore one
of the most important criteria. The maximum ESR can be
simply calculated from:
step current Transient I
excursion voltage transient MaximumV
Where
I
V
R
t
t
t
t
ESR
=
=
For example, to meet a 100mV transient limit with a 10A
load step, the output capacitor ESR must be less than
10m. To meet this kind of ESR level, there are three
available capacitor technologies.
ygolonhceT
.paChcaE
.ytQ
.dqR
latoT
C
(µ )F
RSE
m( )
C
(µ )F
RSE
m( )
mulatnaTRSEwoL033066000201
NOC-SO0335230993.8
munimulARSEwoL005144500573.8
The choice of which to use is simply a cost/performance
issue, with Low ESR Aluminum being the cheapest, but
taking up the most space.
INDUCTORINDUCTOR
INDUCTORINDUCTOR
INDUCTOR - Having decided on a suitable type and value
of output capacitor, the maximum allowable value of in-
ductor can be calculated. Too large an inductor will pro-
duce a slow current ramp rate and will cause the output
capacitor to supply more of the transient load current
for longer - leading to an output voltage sag below the
ESR excursion calculated above.
The maximum inductor value may be calculated from:
()
OINOA
A
t
ESR
VV or V of lesser the is V where
V
I
CR
L
The calculated maximum inductor value assumes 100%
and 0% duty cycle capability, so some allowance must be
made. Choosing an inductor value of 50 to 75% of the
calculated maximum will guarantee that the inductor cur-
rent will ramp fast enough to reduce the voltage dropped
across the ESR at a faster rate than the capacitor sags,
hence ensuring a good recovery from transient with no
additional excursions.
We must also be concerned with ripple current in the out-
put inductor and a general rule of thumb has been to
allow 10% of maximum output current as ripple current.
Note that most of the output voltage ripple is produced by
the inductor ripple current flowing in the output capacitor
ESR. Ripple current can be calculated from:
OSC
IN
L
fL4
V
I
RIPPLE
=
Ripple current allowance will define the minimum permit-
ted inductor value.
POPO
POPO
PO
WER FETSWER FETS
WER FETSWER FETS
WER FETS - The FETs are chosen based on several
criteria, with probably the most important being power
dissipation and power handling capability.
TT
TT
T
OP FETOP FET
OP FETOP FET
OP FET - The power dissipation in the top FET is a combi-
nation of conduction losses, switching losses and bottom
FET body diode recovery losses.
a) Conduction losses are simply calculated as:
IN
O
)on(DS
2
OCOND
V
V
cycle duty =
where
RIP
δ
δ=
b) Switching losses can be estimated by assuming a switch-
ing time, if we assume 100ns then:
2
INOSW
10VIP
=
or more generally,
4
f)tt(VI
P
OSCfrINO
SW
+
=
c) Body diode recovery losses are more difficult to esti-
mate, but to a first approximation, it is reasonable to as-
sume that the stored charge on the bottom FET body di-
ode will be moved through the top FET as it starts to turn
on. The resulting power dissipation in the top FET will be:
OSCINRRRR
fVQP =
To a first order approximation, it is convenient to only con-

SC1189SWTRT

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Switching Controllers PROG SYNCH DC/DC HYST CONTL
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