4
FN8232.8
August 12, 2010
Absolute Maximum Ratings Thermal Information
Voltage on V
DD
, V
BAT
, SCL, SDA, and RESET
pins
(respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Voltage on X1 and X2 pins
(respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V
Latchup (Note 4) . . . . . . . . . . . . . . . . . . . Class II, Level B @ +85°C
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175V
Thermal Resistance (Typical) θ
JA
(°C/W) θ
JC
(°C/W)
8 Ld SOIC Package (Notes 5, 6) . . . . . 115 50
8 Ld TSSOP Package (Notes 5, 6) . . . 140 40
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: Using a max positive pulse of 8.35V on all pins except X1 and
X2, Using a max positive pulse of 2.75V on X1 and X2, and using a max negative pulse of -1V for all pins.
5. θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. For θ
JC
, the “case temp” location is taken at the package top center.
DC Electrical Specifications Unless otherwise noted, V
DD
= +2.7V to +5.5V, T
A
= -40°C to +85°C, Typical values are at T
A
= +25°C and
V
DD
= 3.3V. Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL PARAMETER CONDITIONS
MIN
(Note 16) TYP
MAX
(Note 16) UNIT NOTES
V
DD
Main Power Supply 2.7 5.5 V
V
BAT
Backup Power Supply 1.8 5.5 V
Electrical Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL PARAMETER CONDITIONS
MIN
(Note 16) TYP
MAX
(Note 16) UNIT NOTES
I
DD1
Supply Current with I
2
C Active V
DD
= 2.7V 500 µA 7, 8, 9
V
DD
= 5.5V 800 µA
I
DD2
Supply Current for Non-Volatile
Programming
V
DD
= 2.7V 2.5 mA 7, 8, 9
V
DD
= 5.5V 3.5 mA
I
DD3
Supply Current for Main
Timekeeping (Low Power Mode)
V
DD
= V
SDA
= V
SCL
= 2.7V 10 µA 9
V
DD
= V
SDA
= V
SCL
= 5.5V 20 µA
I
BAT
Battery Supply Current V
BAT
= 1.8V,
V
DD
= V
SDA
= V
SCL
= V
RESET
=0V
800 1000 nA 7, 10, 11
V
BAT
= 3.0V,
V
DD
= V
SDA
= V
SCL
= V
RESET
=0V
850 1200 nA
I
BATLKG
Battery Input Leakage V
DD
= 5.5V, V
BAT
= 1.8V -100 100 nA
V
TRIP
V
BAT
Mode Threshold 1.8 2.2 2.6 V11
V
TRIPHYS
V
TRIP
Hysteresis 30 mV 11, 14
V
BATHYS
V
BAT
Hysteresis 50 mV 11, 14
V
DD SR-
V
DD
Negative Slew rate 10 V/ms 12
RESET
OUTPUT
V
OL
Output Low Voltage V
DD
= 5.5V
I
OL
= 3mA
0.4 V
V
DD
= 2.7V
I
OL
= 1mA
0.4 V
I
LO
Output Leakage Current V
DD
= 5.5V
V
OUT
= 5.5V
100 400 nA
ISL12027, ISL12027A
5
FN8232.8
August 12, 2010
Watchdog Timer/Low Voltage Reset Parameters
SYMBOL PARAMETER CONDITIONS
MIN
(Note 16)
TYP
(Note 5)
MA
(Note 16) UNITS NOTES
t
RPD
V
DD
Detect to RESET LOW 500 ns 13
t
PURST
Power-up Reset Time-Out Delay 100 250 400 ms
V
RVALID
Minimum V
DD
for Valid RESET
Output
1.0 V
V
RESET
ISL12027-4.5A Reset Voltage Level 4.59 4.64 4.69 V
ISL12027 Reset Voltage Level 4.33 4.38 4.43 V
ISL12027-3 Reset Voltage Level 3.04 3.09 3.14 V
ISL12027-2.7A Reset Voltage Level 2.87 2.92 2.97 V
ISL12027-2.7 Reset Voltage Level 2.58 2.63 2.68 V
t
WDO
Watchdog Timer Period 32.768kHz crystal between X1
and X2
1.70 1.75 1.801 s
725 750 775 ms
225 250 275 ms
t
RST
Watchdog Timer Reset Time-Out
Delay
32.768kHz crystal between X1
and X2
225 250 275 ms
t
RSP
I
2
C Interface Minimum Restart Time 1.2 µs
EEPROM SPECIFICATIONS
EEPROM Endurance >2,000,000 Cycles
EEPROM Retention Temperature ≤ +75°C 50 Years
Serial Interface (I
2
C) Specifications
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES
V
IL
SDA, and SCL Input Buffer LOW
Voltage
SBIB = 1 (Under V
DD
mode) -0.3 0.3xV
DD
V
V
IH
SDA, and SCL Input Buffer HIGH
Voltage
SBIB = 1 (Under V
DD
mode) 0.7xV
DD
V
DD
+ 0.3 V
Hysteresis SDA and SCL Input Buffer
Hysteresis
SBIB = 1 (Under V
DD
mode) 0.05xV
DD
V
V
OL
SDA Output Buffer LOW Voltage I
OL
= 4mA 0 0.4 V
I
LI
Input Leakage Current on SCL V
IN
= 5.5V 0.1 10 µA
I
LO
I/O Leakage Current on SDA V
IN
= 5.5V 0.1 10 µA
TIMING CHARACTERISTICS
f
SCL
SCL Frequency 400 kHz
t
IN
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec
is suppressed.
50 ns
t
AA
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30% of V
DD
,
until SDA exits the 30% to 70% of V
DD
window.
900 ns
t
BUF
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of V
DD
during a
STOP condition, to SDA crossing 70%
of V
DD
during the following START
condition.
1300 ns
t
LOW
Clock LOW Time Measured at the 30% of V
DD
crossing. 1300 ns
t
HIGH
Clock HIGH Time Measured at the 70% of V
DD
crossing. 600 ns
ISL12027, ISL12027A
6
FN8232.8
August 12, 2010
t
SU:STA
START Condition Set-up Time SCL rising edge to SDA falling edge.
Both crossing 70% of V
DD
.
600 ns
t
HD:STA
START Condition Hold Time From SDA falling edge crossing 30%
of V
DD
to SCL falling edge crossing
70% of V
DD
.
600 ns
t
SU:DAT
Input Data Set-up Time From SDA exiting the 30% to 70% of
V
DD
window, to SCL rising edge
crossing 30% of V
DD
.
100 ns
t
HD:DAT
Input Data Hold Time From SCL falling edge crossing 70% of
V
DD
to SDA entering the 30% to 70%
of V
DD
window.
0ns
t
SU:STO
STOP Condition Set-up Time From SCL rising edge crossing 70% of
V
DD
, to SDA rising edge crossing 30%
of V
DD
.
600 ns
t
HD:STO
STOP Condition Hold Time for
Read, or Volatile Only Write
From SDA rising edge to SCL falling
edge. Both crossing 70% of V
DD
.
600 ns
t
DH
Output Data Hold Time From SCL falling edge crossing 30% of
V
DD
, until SDA enters the 30% to 70%
of V
DD
window.
0ns
t
R
SDA and SCL Rise Time From 30% to 70% of V
DD
20 +
0.1xCb
250 ns
t
F
SDA and SCL Fall Time From 70% to 30% of V
DD
20 +
0.1xCb
250 ns
Cpin SDA, and SCL Pin Capacitance 10 pF
t
WC
Non-Volatile Write Cycle Time 12 20 ms 14
t
R
SDA and SCL Rise Time From 30% to 70% of V
DD
20 +
0.1xCb
250 ns 15
t
F
SDA and SCL Fall Time From 70% to 30% of V
DD
20 +
0.1xCb
250 ns 15
Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF 15
R
PU
SDA and SCL Bus Pull-up Resistor
Off-chip
Maximum is determined by t
R
and t
F
.
For Cb = 400pF, max is about
2kΩ~2.5kΩ.
For Cb = 40pF, max is about
15kΩ~20kΩ
1kΩ 15
NOTES:
7. RESET
Inactive (no reset).
8. V
IL
= V
DD
x 0.1, V
IH
= V
DD
x 0.9, f
SCL
= 400kHz.
9. V
RESET
= 2.63V (V
DD
must be greater than V
RESET
), V
BAT
= 0V.
10. Bit BSW = 0 (Standard Mode), ATR = 00h, V
BAT
1.8V.
11. Specified at +25°C.
12. In order to ensure proper timekeeping, the V
DD SR-
specification must be followed.
13. Parameter is not 100% tested.
14. t
WC
is the minimum cycle time to be allowed for any non-volatile Write by the user, it is the time from valid STOP condition at the end of Write
sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.
15. These are I
2
C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
16. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
Serial Interface (I
2
C) Specifications (Continued)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES
ISL12027, ISL12027A

ISL12027AIV27Z-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Real Time Clock REAL TIME CLK/CLNDR W/EEPROM 2 63VSET
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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