74LVCH162373APAG Datasheet 74LVCH162373APAG, 74LVCH162373APAG8, 74LVCH162373APVG8 | P1-P3

INDUSTRIAL TEMPERATURE RANGE

IDT74LVCH162373A

3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH

OCTOBER 2015INDUSTRIAL TEMPERATURE RANGE

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FEATURES:

• Typical tSK(o) (Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

•VCC = 3.3V ± 0.3V, Normal Range

•VCC = 2.7V to 3.6V, Extended Range

• CMOS power levels (0.4

μμ

μ W typ. static)

• All inputs, outputs, and I/O are 5V tolerant

• Available in TSSOP package

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS:

• 5V and 3.3V mixed voltage systems

• Data communication and telecommunication systems

DRIVE FEATURES:

• Balanced Output Drivers: ±12mA

• Low switching noise

IDT74LVCH162373A

DESCRIPTION:

The LVCH162373A 16-bit transparent D-type latch is built using ad-

vanced dual metal CMOS technology. This high-speed, low-power latch

is ideal for temporary storage of data. The LVCH162373A can be used for

implementing memory address latches, I/O ports, and bus drivers. The

output enable and latch enable controls are organized to operate each

device as two 8-bit latches or one 16-bit latch. Flow-through organization

of signal pins simplifies layout. All inputs are designed with hysteresis for

improved noise margin.

All pins of the LVCH162373A can be driven from either 3.3V or 5V

devices. This feature allows the use of this device as a translator in a mixed

3.3V/5V supply system.

The LVCH162373A has series resistors in the device output structure

which will significantly reduce line noise when used with light loads. The

driver has been developed to drive ±12mA at the designated threshold

levels.

The LVCH162373A has “bus-hold” which retains the inputs’ last state

whenever the input goes to a high impedance. This prevents floating inputs

and eliminates the need for pull-up/down resistors.

3.3V CMOS 16-BIT

TRANSPARENT D-TYPE LATCH

WITH 3-STATE OUTPUTS, 5 VOLT

TOLERANT I/O, BUS-HOLD

1OE

1LE

1D1

TO SEVEN OTHER CHANNELS

2OE

2LE

2D1

TO SEVEN OTHER CHANNELS

DSC-4888/5

INDUSTRIAL TEMPERATURE RANGE

IDT74LVCH162373A

3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH

TSSOP

TOP VIEW

PIN CONFIGURATION

Symbol Description Max Unit

VTERM Terminal Voltage with Respect to GND –0.5 to +6.5 V

TSTG Storage Temperature –65 to +150 °C

IOUT DC Output Current –50 to +50 mA

IK Continuous Clamp Current, –50 mA

IOK VI < 0 or VO < 0

CC Continuous Current through each ±100 mA

ISS VCC or GND

ABSOLUTE MAXIMUM RATINGS

(1)

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

NOTE:

1. As applicable to the device type.

Symbol Parameter

(1)

Conditions Typ. Max. Unit

CIN Input Capacitance VIN = 0V 4.5 6 pF

COUT Output Capacitance VOUT = 0V 6.5 8 pF

I/O I/O Port Capacitance VIN = 0V 6.5 8 pF

CAPACITANCE (TA = +25°C, F = 1.0MHz)

NOTES:

1. H = HIGH Voltage Level

X = Don’t Care

L = LOW Voltage Level

Z = High-Impedance

2. Output level before the indicated steady-state input conditions were established.

Inputs Outputs

xOE xLE xDx xQx

LHH H

LHL L

LLX Q

(2)

HXX Z

FUNCTION TABLE (EACH 8-BIT SECTION)

(1)

Pin Names Description

xDx Data Inputs

(1)

xLE Latch Enable Inputs (Active HIGH)

x Q x 3-State Outputs

xOE Output Enable Inputs (Active LOW)

PIN DESCRIPTION

NOTE:

1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.

1Q2

GND

481

1Q1

1Q4

VCC

2Q5

GND

2Q7

1D2

GND

1D1

1D4

VCC

2D5

GND

2D7

INDUSTRIAL TEMPERATURE RANGE

IDT74LVCH162373A

3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH

Symbol Parameter Test Conditions Min. Typ.

(1)

Max. Unit

VIH Input HIGH Voltage Level VCC = 2.3V to 2.7V 1.7 — — V

VCC = 2.7V to 3.6V 2 — —

IL Input LOW Voltage Level VCC = 2.3V to 2.7V — — 0.7 V

VCC = 2.7V to 3.6V — — 0.8

IIH Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5 μA

IIL

IOZH High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 μA

IOZL (3-State Output pins)

IOFF Input/Output Power Off Leakage VCC = 0V, VIN or VO ≤ 5.5V — — ±50 μA

VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V

VH Input Hysteresis VCC = 3.3V — 100 — mV

CCL Quiescent Power Supply Current VCC = 3.6V VIN = GND or VCC —— 10μA

ICCH

ICCZ 3.6 ≤ VIN ≤ 5.5V

(2)

—— 10

ΔICC Quiescent Power Supply Current One input at VCC - 0.6V, other inputs at VCC or GND — — 500 μA

Variation

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:

Operating Condition: TA = –40°C to +85°C

NOTES:

1. Typical values are at VCC = 3.3V, +25°C ambient.

2. This applies in the disabled state only.

BUS-HOLD CHARACTERISTICS

Symbol Parameter

(1)

Test Conditions Min. Typ.

(2)

Max. Unit

IBHH Bus-Hold Input Sustain Current VCC = 3V VI = 2V – 75 — — μA

IBHL VI = 0.8V 75 — —

IBHH Bus-Hold Input Sustain Current VCC = 2.3V VI = 1.7V — — — μA

IBHL VI = 0.7V — — —

IBHHO Bus-Hold Input Overdrive Current VCC = 3.6V VI = 0 to 3.6V — — ±500 μA

IBHLO

NOTES:

1. Pins with Bus-Hold are identified in the pin description.

2. Typical values are at VCC = 3.3V, +25°C ambient.

P1-P3 P4-P6

74LVCH162373APAG

Mfr. #:

Buy 74LVCH162373APAG

Manufacturer:

IDT

Description:

Latches 3.3V CMOS 16BIT TRANS LAT

Lifecycle:

New from this manufacturer.

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74LVCH162373APAG

74LVCH162373APAG

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