CY7C68000-56PVXCT

CY7C6800
0
Document #: 38-08016 Rev. *H Page 10 of 14
9.2.2 HS/FS Interface Timing–30 MHz
TCSU_MIN
TCH_MIN
TDSU_MIN
TDH_MIN
TCVO
TCCO
DataIn
DataOut
Control_Out
Control_In
CLK
TCDO
TVSU_MIN
TVH_MIN
Figure 9-2. 30-MHz Timing Interface Timing Constraints
Table 9-2. 30 MHz Timing Interface Timing Constraints Parameters
Parameter Description Min. Typ. Max. Unit Notes
T
CSU_MIN
Minimum set-up time for TXValid 20 ns
T
CH_MIN
Minimum hold time for TXValid 1 ns
T
DSU_MIN
Minimum set-up time for Data (Transmit direction) 20 ns
T
DH_MIN
Minimum hold time for Data (Transmit direction) 1 ns
T
CCO
Clock to Control Out time for TXReady, RXValid,
RXActive and RXError
120ns
T
CDO
Clock to Data out time (Receive direction) 1 20 ns
T
VSU_MIN
Minimum set-up time for ValidH (transmit Direction) 20 ns
T
VH_MIN
Minimum hold time for ValidH (Transmit direction) 1 ns
T
CVO
Clock to ValidH out time (Receive direction) 1 20 ns
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CY7C6800
0
Document #: 38-08016 Rev. *H Page 11 of 14
10.0 Ordering Information
11.0 Package Diagrams
The TX2 is available in two packages:
56-pin SSOP
56-pin QFN.
Table 10-1. Ordering Information
Ordering Code Package Type
CY7C68000-56LFXC 56 QFN (Pb-Free)
CY7C68000-56LFXCT 56 QFN (Pb-Free) Tap/Reel
CY7C68000-56PVC 56 SSOP
CY7C68000-56PVCT 56 SSOP Tape/Reel
CY7C68000-56PVXC 56 SSOP (Pb-Free)
CY7C68000-56PVXCT 56 SSOP (Pb-Free) Tape/Reel
CY3683 EZ-USB TX2 Development Board
51-85062-*C
Figure 11-1. 56-lead Shrunk Small Outline Package O56
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CY7C6800
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Document #: 38-08016 Rev. *H Page 12 of 14
12.0 PCB Layout Recommendations
[3]
The following recommendations should be followed to ensure
reliable high-performance operation.
At least a four-layer impedance controlled boards are
required to maintain signal quality.
Specify impedance targets (ask your board vendor what
they can achieve).
To control impedance, maintain trace widths and trace
spacing to within specifications.
Minimize stubs to minimize reflected signals.
Connections between the USB connector shell and signal
ground must be done near the USB connector.
Bypass/flyback capacitors on VBus, near the connector, are
recommended.
DPLUS and DMINUS trace lengths should be kept to within
2 mm of each other in length, with preferred length of 20–30
mm.
Maintain a solid ground plane under the DPLUS and
DMINUS traces. Do not allow the plane to be split under
these traces.
If possible, do not place any vias on the DPLUS or DMINUS
trace routing.
Isolate the DPLUS and DMINUS traces from all other signal
traces by no less than 10 mm.
Note:
3. Source for recommendations: EZ-USB FX2™ PCB Design Recommendations, http:///www.cypress.com/cfuploads/support/app_notes/FX2_PCB.pdf High-
Speed USB Platform Design Guidelines, http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf.
Figure 11-2. 56-lead Quad Flatpack No Lead Package (8 x 8 mm) (SAWN VERSION)
A
8.10[0.319]
7.90[0.311]
7.90[0.311]
8.10[0.319]
0.20[0.008] REF.
0.04[0.0015] MAX.
C
0.50[0.020]
6.55[0.258]
6.45[0.254]
0.28[0.011]
0.18[0.007]
6.55[0.258]
6.45[0.254]
SEATING
PLANE
C0.08[0.003]
0.30[0.012]
0.50[0.020]
1.00[0.039] MAX.
TOP VIEW
BOTTOM VIEW
SIDE VIEW
PIN #1
CORNER
PIN #1
CORNER
E-PAD
(PAD SIZE VARY
BY DEVICE TYPE)
DIMENSIONS IN MM[INCHES] MIN.
MAX.
REFERENCE JEDEC MO-220
51-85187-*A
56-Lead QFN 8 x 8 mm (Sawn Version) LS56B
E-PAD maximum size
4.75 X 5.46 mm [187 x 215 mils] (width x length).
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CY7C68000-56PVXCT

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
IC USB 2.0 TX2 TXRX 56-SSOP
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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