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8533AGI-01LF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
8533I-01 DATA SHEET
4 REVISION A 7/9/15
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
CC
= 3.3V±5%, TA = -40°C TO 85°C
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, V
CC
= 3.3V±5%, TA = -40°C TO 85°C
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V
CC
= 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
CC
Positive Supply Voltage 3.135 3.3 3.465 V
I
EE
Power Supply Current 52 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage 2 V
CC
+ 0.3 V
V
IL
Input Low Voltage -0.3 0.8 V
I
IH
Input High Current
CLK_EN V
IN
= V
CC
= 3.465V 5 µA
CLK_SEL V
IN
= V
CC
= 3.465V 150 µA
I
IL
Input Low Current
CLK_EN V
IN
= 0V, V
CC
= 3.465V -150 µA
CLK_SEL V
IN
= 0V, V
CC
= 3.465V -5 µA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High Current
nCLK V
CC
= V
IN
= 3.465V 5 µA
CLK V
CC
= V
IN
= 3.465V 150 µA
I
IL
Input Low Current
nCLK V
CC
= 3.465V, V
IN
= 0V -150 µA
CLK V
CC
= 3.465V, V
IN
= 0V -5 µA
V
PP
Peak-to-Peak Input Voltage 0.15 1.3 V
V
CMR
Common Mode Input Voltage;
NOTE 1, 2
V
EE
+ 0.5 V
CC
- 0.85 V
NOTE 1: For single ended applications, the maximum input voltage for CLK and nCLK is V
CC
+ 0.3V.
NOTE 2: Common mode voltage is defi ned as V
IH
.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current 50mA
Surge Current 100mA
Package Thermal Impedance, θ
JA
73.2°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifi cations only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Charac-
teristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
REVISION A 7/9/15
8533I-01 DATA SHEET
5 LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS, V
CC
= 3.3V±5%, TA = -40°C TO 85°C
TABLE 5. AC CHARACTERISTICS, V
CC
= 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High Current
PCLK V
CC
= V
IN
= 3.465V 150 µA
nPCLK V
CC
= V
IN
= 3.465V 5 µA
I
IL
Input Low Current
PCLK V
CC
= 3.465V, V
IN
= 0V -5 µA
nPCLK V
CC
= 3.465V, V
IN
= 0V -150 µA
V
PP
Peak-to-Peak Input Voltage 0.3 1 V
V
CMR
Common Mode Input Voltage; NOTE 1, 2 V
EE
+ 1.5 V
CC
V
V
OH
Output High Voltage; NOTE 3 V
CC
- 1.4 V
CC
- 0.9 V
V
OL
Output Low Voltage; NOTE 3 V
CC
- 2.0 V
CC
- 1.7 V
V
SWING
Peak-to-Peak Output Voltage Swing 0.6 1.0 V
NOTE 1: Common mode voltage is defi ned as V
IH
.
NOTE 2: For single ended applications the maximum input voltage for PCLK and nPCLK is V
CC
+ 0.3V.
NOTE 3: Outputs terminated with 50Ω to V
CC
- 2V.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 650 MHz
t
PD
Propagation Delay;
NOTE 1
CLK, nCLK 1.15 1.5 ns
PCLK, nPCLK 1.0 1.3 ns
tsk(o) Output Skew; NOTE 2, 4 30 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4 150 ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
0.060 ps
t
R
/ t
F
Output Rise/Fall Time 300 800 ps
odc Output Duty Cycle 47 53 %
All parameters measured at f £ 650MHz unless noted otherwise.
The cycle to cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defi ned as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65.
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
8533I-01 DATA SHEET
6 REVISION A 7/9/15
ADDITIVE PHASE JITTER
Input/Output Additive
Phase Jitter at 156.25MHz
= 0.060ps (typical)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-
160
-170
-180
-
190
1k 10k 100k 1M 10M 100M
The spectral purity in a band at a specifi c offset from the
fundamental compared to the power of the fundamental is
called the dBc Phase Noise. This value is normally expressed
using a Phase noise plot and is most often the specifi ed plot
in many applications. Phase noise is defi ned as the ratio of the
noise power present in a 1Hz band at a specifi ed offset from the
fundamental frequency to the power value of the fundamental.
This ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifi cations, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise fl oor of the equipment is higher
than the noise fl oor of the device. This is illustrated above. The
the 1Hz band to the power in the fundamental. When the required
offset is specifi ed, the phase noise is called a dBc value, which
simply means dBm at a specifi ed offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
device meets the noise fl oor of what is shown, but can actually
be lower. The phase noise is dependent on the input source and
measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB PHASE NOISE dBc/HZ
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

8533AGI-01LF

Mfr. #:
Buy 8533AGI-01LF
Manufacturer:
IDT
Description:
Clock Buffer 1-to-4 LVPECL Fanout Buffer
Lifecycle:
New from this manufacturer.
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