1/12November 2004
■ HIGH SPEED: t
PD
= 5.7ns (TYP.) at V
CC
= 5V
■ LOW POWER DISSIPATION:
I
CC
= 4 µA (MAX.) at T
A
=25°C
■ HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
■ POWER DOWN PROTECTION ON INPUTS
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
■ BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL
■ OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138
■ IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74VHC138 is an advanced high-speed
CMOS 3 TO 8 LINE DECODER (INVERTING)
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology.
If the device is enabled, 3 binary select (A, B, and
C) determine which one of the outputs will go low.
If enable input G1 is held low or either G2A
or G2B
is held high, the decoding function is inhibited and
all the 8 outputs go to high.
Tree enable inputs are provided to ease cascade
connection and application of address decoders
for memory systems.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74VHC138
3 TO 8 LINE DECODER (INVERTING)
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE T & R
SOP 74VHC138MTR
TSSOP 74VHC138TTR
TSSOPSOP
Rev. 4
