ESD7410N2T5G

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4
IEC 61000−4−2 Spec.
Level
Test Volt-
age (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8
I
peak
90%
10%
IEC61000−4−2 Waveform
100%
I @ 30 ns
I @ 60 ns
t
P
= 0.7 ns to 1 ns
Figure 7. IEC61000−4−2 Spec
Figure 8. Diagram of ESD Clamping Voltage Test Setup
50 W
50 W
Cable
TVS
Oscilloscope
ESD Gun
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD7410, SZESD7410
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5
Figure 9. Positive TLP I−V Curve
Figure 10. Negative TLP I−V Curve
NOTE: TLP parameter: Z
0
= 50 W, t
p
= 100 ns, t
r
= 300 ps, averaging window: t
1
= 30 ns to t
2
= 60 ns. V
IEC
is the equivalent voltage
stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description
below for more information.
V
C
, CLAMPING VOLTAGE (V) V
C
, CLAMPING VOLTAGE (V)
20151050
0
2
6
10
12
16
20
−20−15−10−50
0
−2
−6
−8
−10
−14
−18
−20
TLP CURRENT (A)
TLP CURRENT (A)
25
4
8
14
18
−25
−4
−12
−16
0
6
8
10
2
4
EQUIVALENT VIEC (kV)
0
−6
−8
−10
−2
−4
EQUIVALENT VIEC (kV)
Transmission Line Pulse (TLP) Measurement
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 11. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 12 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
Figure 11. Simplified Schematic of a Typical TLP
System
DUT
L
S
÷
Oscilloscope
Attenuator
10 MW
V
C
V
M
I
M
50 W Coax
Cable
50 W Coax
Cable
Figure 12. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
ESD7410, SZESD7410
www.onsemi.com
6
PACKAGE DIMENSIONS
X2DFN2 1.0x0.6, 0.65P
CASE 714AB
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. EXPOSED COPPER ALLOWED AS SHOWN.
A B
E
D
BOTTOM VIEW
b
L
0.10
C
TOP VIEW
0.05
C
A
A1
0.10 C
0.10 C
C
SEATING
PLANE
SIDE VIEW
DIM MIN MAX
MILLIMETERS
A 0.34 0.40
A1 −− 0.05
b 0.45 0.55
D 1.00 BSC
E 0.60 BSC
SOLDER FOOTPRINT*
DIMENSIONS: MILLIMETERS
1.20
0.60
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
1
L 0.20 0.30
0.47
RECOMMENDED
PIN 1
PIN 1
INDICATOR
e 0.65 BSC
A
M
0.05 BC
A
M
0.05 BC
2X
e
e/2
2X
2X
NOTE 3
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ESD7410N2T5G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
TVS Diodes / ESD Suppressors 10V VRWM ESD PROTECTION
Lifecycle:
New from this manufacturer.
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