MC100EP131MNG

© Semiconductor Components Industries, LLC, 2006
November, 2006 Rev. 10
1 Publication Order Number:
MC10EP131/D
MC10EP131, MC100EP131
3.3V / 5VECL Quad D
Flip−Flop with Set, Reset,
and Differential Clock
Description
The MC10/100EP131 is a Quad Masterslaved D flipflop with
common set and separate resets. The device is an expansion of the
E131 with differential common clock and individual clock enables.
With AC performance faster than the E131 device, the EP131 is ideal
for applications requiring the fastest AC performance available.
Each flipflop may be clocked separately by holding Common
Clock (C
C
) LOW and C
C
HIGH, then using the differential Clock
Enable inputs for clocking (C
03
, C
03
).
Common clocking is achieved by holding the differential inputs
C
03
LOW and C
03
HIGH while using the differential Common
Clock (C
C
) to clock all four flipflops. When left floating open, any
differential input will disable operation due to input pulldown resistors
forcing an output default state.
Individual asynchronous resets (R
03
) and an asynchronous set
(SET) are provided.
Data enters the master when both C
C
and C
03
are LOW, and
transfers to the slave when either C
C
or C
03
(or both) go HIGH.
The 100 Series contains temperature compensation.
Features
460 ps Typical Propagation Delay
Maximum Frequency > 3 GHz Typical
Differential Individual and Common Clocks
Individual Asynchronous Resets
Asynchronous Set
PECL Mode Operating Range: V
CC
= 3.0 V to 5.5 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= 3.0 V to 5.5 V
Open Input Default State
Safety Clamp on Inputs
Q Output Will Default LOW with Inputs Open or at V
EE
PbFree Packages are Available
LQFP32
FA SUFFIX
CASE 873A
MARKING
DIAGRAM*
*For additional marking information, refer to
Application Note AND8002/D.
http://onsemi.com
MCxxx
EP131
AWLYYWWG
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
32
1
MCxxx
EP131
AWLYYWWG
G
1
QFN32
MN SUFFIX
CASE 488AM
xxx = 10 or 100
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = PbFree Package
(Note: Microdot may be in either location)
MC10EP131, MC100EP131
http://onsemi.com
2
V
EE
25
26
27
28
29
30
31
32
15
14
13
12
11
10
9
12345678
24 23 22 21 20 19 18 17
16
R
1
C
0
C
0
V
CC
D
0
R
0
V
CC
D
2
SET
R
3
D
3
V
EE
C
3
C
3
V
CC
D
1
C
1
C
1
C
C
C
C
C
2
R
2
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
32Lead LQFP Pinout
(Top View)
C
2
Table 1. PIN DESCRIPTION
PIN
D
03
* ECL Data Inputs
FUNCTION
C
03
*, C
03
*
C
C
*, C
C
* ECL Common Clock Inputs
ECL Separate Clock Inputs
R
03
* ECL Asynchronous Reset
SET* ECL Asynchronous Set
Q
03
, Q
03
ECL Data Outputs
V
CC
Positive Supply
V
EE
Negative Supply
D
3
C
3
R
3
D
2
C
2
R
2
SET
C
C
R
1
C
1
D
1
R
0
C
0
D
0
Q
3
Q
3
Q
2
Q
2
Q
1
Q
1
Q
0
Q
0
S
D
Q
Q
R
S
D
Q
Q
R
R
D
Q
Q
S
R
D
Q
Q
S
C
3
C
2
C
1
C
0
C
C
Figure 1. 32Lead LQFP Pinout (Top View)
Warning: All V
CC
and V
EE
pins must be externally connected
to Power Supply to guarantee proper operation.
* Pins will default LOW when left open.
V
EE
D
L
H
X
X
X
Table 2. TRUTH TABLE
S*
L
L
H
L
H
R*
L
L
L
H
H
CLK
Z
Z
X
X
X
Q
L
H
H
L
Undef
Z = LOW to HIGH Transition
* Pins will default low when left open.
The Exposed Pad (EP) on the
QFN32 package bottom is
thermally connected to the die
for improved heat transfer out
of package. The exposed pad
must be attached to a heat
sinking conduit. The pad is
electrically connected to V
EE
.
EP for
QFN32, only
V
EE
2526272829303132
1514131211109
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
R1 C0 C0 V
CC
D0 R0 V
CC
D2 SET R3 D3 V
EE
C3 C3 V
CC
D1
CC
R2
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
C2
CC
C1
C1
C2
Figure 2. 32Lead QFN Pinout (Top View)
Figure 3. Logic Diagram
MC10EP131
MC100EP131
MC10EP131, MC100EP131
http://onsemi.com
3
Table 3. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor N/A
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 100 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg PbFree Pkg
LQFP32
QFN32
Level 2 Level 2
Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 @ 0.125 in
Transistor Count 935 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
PECL Mode Power Supply V
EE
= 0 V 6 V
V
EE
NECL Mode Power Supply V
CC
= 0 V 6 V
V
I
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
= 0 V
V
CC
= 0 V
V
I
V
CC
V
I
V
EE
6
6
V
V
I
out
Output Current Continuous
Surge
50
100
mA
mA
I
BB
V
BB
Sink/Source ± 0.5 mA
T
A
Operating Temperature Range 40 to +85 °C
T
stg
Storage Temperature Range 65 to +150 °C
q
JA
Thermal Resistance (JunctiontoAmbient) 0 lfpm
500 lfpm
32 LQFP
32 LQFP
80
55
°C/W
°C/W
q
JC
Thermal Resistance (JunctiontoCase) Standard Board 32 LQFP 12 to 17 °C/W
q
JA
Thermal Resistance (JunctiontoAmbient) 0 lfpm
500 lfpm
QFN32
QFN32
31
27
°C/W
°C/W
q
JC
Thermal Resistance (JunctiontoCase) 2S2P QFN32 12 °C/W
T
sol
Wave Solder Pb
PbFree
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

MC100EP131MNG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Flip Flops BBG ECL 4BIT
Lifecycle:
New from this manufacturer.
Delivery:
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