780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
84320-01 DATA SHEET
10 REVISION D 5/26/16
CRYSTAL INPUT INTERFACE
A crystal can be characterized for either series or parallel mode
operation. The 84320-01 has a built-in crystal oscillator circuit.
This interface can accept either a series or parallel crystal
without additional components and generate frequencies with
FIGURE 3. CRYSTAL INPUt INTERFACE
accuracy suitable for most applications. Additional accuracy
can be achieved by adding two small capacitors C1 and C2 as
shown in Figure 3.
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 4. The XTAL_OUT pin can be left fl oating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs,
it is recommended that the amplitude be reduced from full
swing to half swing in order to prevent signal interference with
the power rail and to reduce noise. This confi guration requires
FIGURE 4. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In
addition, matched termination at the crystal input will attenuate
the signal in half. This can be done in one of two ways. First, R1
and R2 in parallel should equal the transmission line impedance.
For most 50Ω applications, R1 and R2 can be 100Ω. This can
also be accomplished by removing R1 and making R2 50Ω.
REVISION D 5/26/16
84320-01 DATA SHEET
11 780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50Ω transmission lines. Matched impedance techniques
FIGURE 5B. LVPECL OUTPUT TERMINATIONFIGURE 5A. LVPECL OUTPUT TERMINATION
should be used to maximize operating frequency and minimize
signal distortion. Figures 5A and 5B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
TERMINATION FOR LVPECL OUTPUTS
780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
84320-01 DATA SHEET
12 REVISION D 5/26/16
The schematic of the 84320-01 layout example used in this
layout guideline is shown in Figure 6A. The 84320-01 recom-
mended PCB board layout for this example is shown in Figure
6B. This layout example is used as a general guideline. The
LAYOUT GUIDELINE
FIGURE 6A. SCHEMATIC OF RECOMMENDED LAYOUT
layout in the actual system will depend on the selected compo-
nent types, the density of the components, the density of the
traces, and the stack up of the P.C. board.
R4
84
C16
10u
+
-
C11
0.01u
REF_IN
C14
0.1u
VCC
IN+
TL1
Zo = 50 Ohm
C1
S_CLOCK
VCCA
VCC
FOUT
VCC
U1
ICS84320-01
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
M5
M6
M7
M8
N0
N1
nc
VEE
TEST
VCC
FOUT1
nFOUT1
VCCO
FOUT0
nFOUT0
VEE
MR
S_CLOCK
S_DATA
S_LOAD
VCCA
nXTAL_SEL
T_CLK
XTAL2
M4
M3
M2
M1
M0
VCO_SEL
nP_LOAD
XTAL1
S_DATA
TL2
Zo = 50 Ohm
X1
C2
S_LOAD
R7
24
XTAL_SEL
FOUTN
IN-
R3
125
R1
125
R2
84
C15
0.1u
VCC

84320AY-01LNT

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IC SYNTHESIZER 780MHZ 32-LQFP
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