DS1236
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additional
NMI pulses. In this way, the ST pin can be used to allow the CMOS processor to determine if
the supply voltage, as monitored by the IN pin, is above or below a selected operating value. This is
illustrated in Figure 3. As discussed above, the RC pin determines the timing relationships and levels of
several signals. The following section describes the power-up and power-down timing diagrams in more
detail.
TIMING DIAGRAMS
This section provides a description of the timing diagrams shown in Figure 10, Figure 11, Figure 12, and
Figure 13. These diagrams show the relative timing and levels in both the NMOS and the CMOS mode
for power-up and down. Figure 10 illustrates the relationship for power-down in CMOS mode. As V
CC
falls, the IN pin voltage drops below V
TP
. As a result, the processor is notified of an impending power
failure via an active
NMI , which allows it to enter a sleep mode. As the power falls further, V
CC
crosses
V
CCTP
, the power monitor trip point. Since the DS1236 is in CMOS mode, no reset is generated. The RST
voltage will follow V
CC
down, but will fall no further than V
BAT
. At this time, CEO is brought high to
write protect the RAM. When the V
CC
reaches V
BAT
, a power-fail is issued via the PF and PF pins.
Figure 11 illustrates operation of the power-down sequence in NMOS mode. Once again, as power falls,
an
NMI is issued. This gives the processor time to save critical data in nonvolatile SRAM. When V
CC
reaches V
CCTP
, an active RST and RST are given. The RST voltage will follow V
CC
as it falls. CEO , PF,
and
PF will operate in a similar manner to CMOS mode. Notice that the NMI will tri-state to prevent a
loss of battery power.
Figure 12 shows the power-up sequence for the NMOS mode. As V
CC
slews above V
BAT
, the PF and
PF
pins are deactivated. An active reset occurs as well as an
NMI . Although the NMI may be short due to
slew rates, reset will be maintained for the standard t
RST
timeout period. At a later time, if the IN pin falls
below V
TP
, a new NMI will occur. If the processor does not issue a ST , a watchdog reset will also occur.
The second
NMI and RST are provided to illustrate these possibilities.
Figure 13 illustrates the power-up timing for CMOS mode. The principal difference is that the DS1236
issues a reset immediately in the NMOS mode. In CMOS mode, a reset is issued when IN rises above
V
TP
. Depending on the processor type, the NMI may terminate the Stop mode in the processor.
WAKE CONTROL/SLEEP CONTROL
The Wake/Sleep Control input (WC/SC ) allows the processor to disable all comparators on the DS1236
before entering the Stop mode. This feature allows the DS1236, processor, and static RAM to maintain
nonvolatility in the lowest power mode possible. The processor may invoke the sleep mode in battery
operated applications to conserve battery capacity when an absence of activity is detected. The operation
of this signal is shown in Figure 14. The DS1236 may subsequently be restarted by a high-to-low
transition on the
PBRST input through human interface via a keyboard, touchpad, etc. The processor will
then be restarted as the watchdog times out and drives RST and
RST active. The DS1236 can also be
started up by forcing the WC/
SC pin high from an external source. Also, if the DS1236 is placed in a
sleep mode by the processor and system power is lost, the DS1236 will wake up the next time V
CC
rises
above V
BAT
. These possibilities are illustrated in Figure 15.
When the sleep mode is invoked during normal power-valid conditions, all operation on the DS1236 is
disabled, thus leaving the
NMI , RST, and RST outputs disabled as well as the ST and IN inputs.
However, a loss of power during a sleep mode will result in an active RST and
RST when the RC pin is
grounded (NMOS mode). If the RC pin is tied high, the RST and
RST pins will remain inactive during
