4
AT88SC0204C
2022DS–SMEM–04/03
Configuration Zone The configuration zone consists of 2048 bits of EEPROM memory used for storing pass-
words, keys and codes and defining security levels to be used for each user zone.
Access rights to the configuration zone are defined in the control logic and may not be
altered by the user.
Security Fuses There are three fuses on the device that must be blown during the device personaliza-
tion process. Each fuse locks certain portions of the configuration zone as OTP
memory. Fuses are designed for the module manufacturer, card manufacturer and card
issuer and should be blown in sequence, although all programming of the device and
blowing of the fuses may be performed at one final step.
Table 3. Configuration Zone
Component Address
Answer to Reset $00
Fab Code
Memory Test Zone
Card Manufacturers Code
Lot History Code
Device Configuration Register $18
Identification Number
Access Registers
Password/Key Registers
Issuer Code
Authentication Attempts Counters $50
Cryptograms
Session Encryption Keys
Secret Seeds
Password Attempts Counters $B0
Write Passwords
Read Passwords
Reserved
5
AT88SC0204C
2022DS–SMEM–04/03
Protocol Selection The AT88SC0204C supports two different communication protocols.
Smart Card Applications: The asynchronous T = 0 protocol defined by ISO 7816-3
is used for compatibility with the industry’s standard smart card readers.
Embedded Applications: A 2-wire serial interface is used for fast and efficient
communication with logic or controllers.
The power-up sequence determines which of the two communication protocols will be
used.
Asynchronous
T = 0 Protocol
This power-up sequence complies with ISO 7816-3 for a cold reset in smart card
applications.
•V
CC
goes high; RST, I/O-SDA and CLK-SCL are low.
Set I/O-SDA in receive mode.
Provide a clock signal to CLK-SCL.
RST goes high after 400 clock cycles.
The device will respond with a 64-bit ATR code, including historical bytes to indicate the
memory density within the CryptoMemory family. Once the asynchronous mode has
been selected, it is not possible to switch to the synchronous mode without powering off
the device.
Figure 2. Asynchronous T = 0 Protocol
Synchronous
2-wire Serial Interface
The synchronous mode is the default after powering up V
CC
due to the internal pull-up
on RST. For embedded applications using CryptoMemory in standard plastic packages,
this is the only communication protocol.
Power-up V
CC
, RST goes high also.
After stable V
CC
, CLK-SCL and I/O-SDA may be driven.
Figure 3. Synchronous 2-wire Protocol
Note: Five clock pulses must be sent before the first command is issued.
V
cc
I/O-SDA
RST
CLK-SCL
AT R
V
cc
I/O-SDA
RST
CLK-SCL
1
2
3
45
6
AT88SC0204C
2022DS–SMEM–04/03
Communication
Security Modes
Communications between the device and host operate in three basic modes. Standard
mode is the default mode for the device after power-up. Authentication mode is acti-
vated by a successful authentication sequence. Encryption mode is activated by a
successful encryption activation following a successful authentication.
Note: 1. Configuration data include viewable areas of the Configuration Zone except the passwords:
MDC: Modification Detection Code.
MAC: Message Authentication Code.
Security Options
Anti-tearing In the event of a power loss during a write cycle, the integrity of the device’s stored data
may be recovered. This function is optional: the host may choose to activate the anti-
tearing function, depending on application requirements. When anti-tearing is active,
write commands take longer to execute, since more write cycles are required to com-
plete them, and data are limited to eight bytes.
Data are written first to a buffer zone in EEPROM instead of the intended destination
address, but with the same access conditions. The data are then written in the required
location. If this second write cycle is interrupted due to a power loss, the device will
automatically recover the data from the system buffer zone at the next power-up.
In 2-wire mode, the host is required to perform ACK polling for up to 20 ms after write
commands when anti-tearing is active. At power-up, the host is required to perform ACK
polling, in some cases for up to 10 ms, in the event that the device needs to carry out the
data recovery process.
Write Lock If a user zone is configured in the write lock mode, the lowest address byte of an 8-byte
page constitutes a write access byte for the bytes of that page.
Example: The write lock byte at $080 controls the bytes from $080 to $087.
The write lock byte may also be locked by writing its least significant (rightmost) bit to
“0”. Moreover, when write lock mode is activated, the write lock byte can only be pro-
grammed – that is, bits written to “0” cannot return to “1”.
In the write lock configuration, only one byte can be written at a time. Even if several
bytes are received, only the first byte will be taken into account by the device.
Table 4. Communication Security Modes
(1)
Mode Configuration Data User Data Passwords Data Integrity Check
Standard Clear Clear Clear MDC
(1)
Authentication Clear Clear Encrypted MAC
(1)
Encryption Clear Encrypted Encrypted MAC
(1)
$080 $081 $082 $083 $084 $085 $086 $087 @
11011001
xxxx xxxx
locked
xxxx xxxx
locked
xxxx xxxx xxxx xxxx
xxxx xxxx
locked
xxxx xxxx xxxx xxxx $80

AT88SC0204C-CI

Mfr. #:
Manufacturer:
Description:
IC EEPROM 2K I2C 5MHZ 8LAP
Lifecycle:
New from this manufacturer.
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