AD8250-EVALZ Datasheet AD8250-EVALZ | P1-P3

Evaluation Board for G = 1, 2, 5, 10;

10 MHz, 20 V/μs Programmable Gain In-Amp

AD8250-EVALZ

Rev. 0

Evaluation boards are only intended for device evaluation and not for production purposes.

Evaluation boards are supplied “as is” and without warranties of any kind, express, implied, or

statutory including, but not limited to, any implied warranty of merchantability or fitness for a

particular purpose. No license is granted by implication or otherwise under any patents or other

intellectual property by application or use of evaluation boards. Information furnished by Analog

Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result

from its use. Analog Devices reserves the right to change devices or specifications at any time

without notice. Trademarks and registered trademarks are the property of their respective owners.

Evaluation boards are not authorized to be used in life support devices or systems.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

Quick evaluation

On-board gain control switches

SMA connectors for high speed gain testing

GENERAL DESCRIPTION

The AD8250-EVALZ is designed to enable quick evaluation of

the AD8250 programmable gain instrumentation amplifier

(PGIA). The evaluation board includes on-board gain setting

switches to quickly demonstrate the AD8250’s software gain

programmability. In addition, an external logic generator can be

connected to the AD8250-EVALZ SMA ports to test the PGIA’s

gain control.

06701-001

TP4

TP5

TP3

VOUT

TP1

DGND

2kΩ

AD8250

SW1

SW2

–V

0.1µF

VREF

JP1

IN–

TP2

R3 R5

IN+

OUT

10µF

–V

10µF

DGND

JP3

C10

GND2

ND1

0Ω

HI TP6

0.1µF

TP7

ADR392

–V

Figure 1. Schematic

AD8250-EVALZ

Rev. 0 | Page 2 of 4

EVALUATION BOARD HARDWARE

QUICK START GUIDE

By default, the AD8250-EVALZ is configured for gain change

using the on-board switches, SW1 and SW2, as shown in

Table 1.

Table 1. Gain Setting Using the On-Board Switches

W3 (Jumper) SW2 SW1 Gain

In place Low Low 1

In place Low High 2

In place High Low 5

In place High High 10

Table 2. Default Settings (From the Factory)

Name Default Status

W1, W2, W3 In place (tied)

JP1, JP3, R1, R2, R3, R5 Shorted by design (on trace)

USING EXTERNAL LOGIC TO CHANGE GAIN

The AD8250-EVALZ accepts external logic signals such as

those from logic generators or FPGAs. To change gains using

external logic signals, Jumpers W1, W2, and W3 must be

removed. Only then will the A0, A1, and

pins on the

AD8250 be directly tied to TP3, TP4, and TP5 (and to the

respective SMA connectors). External logic can be tied via the

test points TP3, TP4 and TP5, or via the respective SMA

connector.

TERMINATION

The AD8250-EVALZ has 50 Ω traces leading to the A0, A1, and

pins. However, it does not have terminations to those pins.

If terminations are added, remove Jumper W1, Jumper W2, and

Jumper W3.

RFI FILTER

An RFI filter pattern is included at the input traces of the

AD8250-EVALZ. R1 and R2 are shorted. The shorted traces

must be cut before R1 and R2 are placed on the board.

OUTPUT FILTER

An output filter pattern is included at the output trace of the

AD8250-EVALZ. To use R3 or R5 in a filter, cut the shorted

traces prior to placing resistors in those locations.

REFERENCE

To level shift the output, a nonzero reference voltage can be applied

to REF. By default, REF is tied to analog GND. Cutting the trace

at JP1 opens the connection between REF and analog GND.

ANALOG AND DIGITAL GROUND

Analog and digital grounds are tied at JP3. To sever the

connection between them, JP3 can be cut with a knife to open

the connection between the two grounds.

GAIN SELECTION (FROM AD8250 DATA SHEET)

This section shows users how to configure the AD8250 for basic

operation. Logic low and logic high voltage limits are listed in

the Specifications section of the

AD8250 data sheet. Typically,

logic low is 0 V and logic high is 5 V; both voltages are meas-

ured with respect to DGND. Refer to the specifications table of

the

AD8250 for the permissible voltage range of DGND. The

gain of the AD8250 can be set using two methods.

Transparent Gain Mode

The easiest way to set the gain is to program it directly via a

logic high or logic low voltage applied to A0 and A1.

Figure 2

shows an example of this gain setting method, referred to through-

out the data sheet as transparent gain mode. Tie

to the

negative supply to engage transparent gain mode. (On the

AD8250-EVALZ board, put the W3 jumper in place.) In this

mode, any change in voltage applied to A0 and A1 from logic

low to logic high, or vice versa, immediately results in a gain

change.

Table 3 is the truth table for transparent gain mode and

Figure 2 shows the AD8250 configured in transparent gain mode.

+15

–15V

+IN

+5V

–IN

10μF0.1µF

G = 10

DGND DGND

REF

AD8250

06701-002

NOTE:

1. IN TRANSPARENT GAIN MODE, WR IS TIED TO −

THE VOLTAGE LEVELS ON A0 AND A1 DETERMINE

THE GAIN. IN THIS EXAMPLE, BOTH A0 AND A1 ARE

SET TO LOGIC HIGH, RESULTING IN A GAIN OF 10.

Figure 2. Transparent Gain Mode, A0 and A1 = High, G = 10

Table 3. Truth Table Logic Levels for Transparent Gain Mode

(W3) A1 (SW2) A0 (SW1) Gain

−V

(in place) Low Low 1

−V

(in place) Low High 2

−V

(in place) High Low 5

−V

(in place) High High 10

AD8250-EVALZ

Rev. 0 | Page 3 of 4

Latched Gain Mode

Some applications have multiple programmable devices such as

multiplexers or other programmable gain instrumentation

amplifiers on the same PCB. In such cases, devices can share a

data bus. The gain of the AD8250 can be set using

as a latch,

allowing other devices to share A0 and A1.

Figure 3 shows a

schematic using this method, known as latched gain mode. (On

the AD8250-EVALZ, remove the W1, W2, and W3 jumpers,

and drive A0, A1, and

with external logic to test this gain

setting mode.) The AD8250 is in this mode when

is held

at logic high or logic low, typically 5 V and 0 V, respectively.

The voltages on A0 and A1 are read on the downward edge

of the

signal as it transitions from logic high to logic low.

This latches in the logic levels on A0 and A1, resulting in a gain

change. See the truth table listing in

Table 4 for more informa-

tion on these gain changes.

+15

–15V

+IN

–IN

10μF0.1µF

DGND DGND

REF

AD8250

+5V

G = PREVIOUS

STATE

G = 10

06701-003

–

NOTE:

1. ON THE DOWNWARD EDGE OF WR, AS IT TRANSITIONS

FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A0

AND A1 ARE READ AND LATCHED IN, RESULTING IN A

GAIN CHANGE. IN THIS EXAMPLE, THE GAIN SWITCHES TO G = 10.

Figure 3. Latched Gain Mode, G = 10

Table 4. Truth Table Logic Levels for Latched Gain Mode

Gain

High to low Low Low Change to 1

High to low Low High Change to 2

High to low High Low Change to 5

High to low High High Change to 10

Low to low X

No change

Low to high X

No change

High to high X

No change

Jumper W1, Jumper W2, and Jumper W3 must be removed and external

logic must be used to test latched gain mode.

X = Don’t care.

On power-up, the AD8250 defaults to a gain of 1 when in

latched gain mode. In contrast, if the AD8250 is configured in

transparent gain mode, it starts at the gain indicated by the

voltage levels on A0 and A1 upon power-up.

Timing for Latched Gain Mode

In latched gain mode, logic levels at A0 and A1 have to be held

for a minimum setup time, t

, before the downward edge of

latches in the gain. Similarly, they must be held for a

minimum hold time of t

after the downward edge of

ensure that the gain is latched in correctly. After t

, A0 and A1

may change logic levels but the gain does not change (until the

next downward edge of

). The minimum duration that

can be held high is t

-HIGH

, and t

-LOW

is the minimum

duration that

can be held low. Digital timing specifications

are listed in the Specification section of the AD8250 data sheet.

The time required for a gain change is dominated by the settling

time of the amplifier. A timing diagram is shown in

Figure 4.

When sharing a data bus with other devices, logic levels applied

to those devices can potentially feed through to the output of

the AD8250. Feedthrough can be minimized by decreasing the

edge rate of the logic signals. Furthermore, careful layout of the

PCB also reduces coupling between the digital and analog

portions of the board.

A0, A1

WR-HIGH

WR-LOW

6701-004

Figure 4. Timing Diagram for Latched Gain Mode

P1-P3 P4-P4

AD8250-EVALZ

Mfr. #:

Buy AD8250-EVALZ

Manufacturer:

Analog Devices Inc.

Description:

Amplifier IC Development Tools AD8250 EVAL BRD

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet

AD8250-EVALZ