7
FN6043.3
January 23, 2006
FIGURE 3A. MEASUREMENT POINTS
Repeat test for other switches. C
L
includes fixture and stray
capacitance.
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. R
ON
TEST CIRCUIT
FIGURE 6. CAPACITANCE TEST CIRCUIT
Test Circuits and Waveforms (Continued)
80%
3V
0V
t
D
LOGIC
INPUT
SWITCH
OUTPUT
0V
V
OUT
t
r
< 20ns
t
f
< 20ns
LOGIC
INPUT
ADD1
COM
R
L
C
L
V
OUT
35pF
300
NO0-NO3
GND
ADD2
V+
V+
C
C
INH
ANALYZER
R
L
SIGNAL
GENERATOR
V+
C
0V or V+
NO or NC
COM
ADDX
GND
INH
0V or V+
V+
C
0V or V+
NO or NC
COM
ADDX
GND
V
NX
V
1
R
ON
= V
1
/1mA
1mA
INH
V+
C
GND
NO or NC
COM
ADDX
IMPEDANCE
ANALYZER
0V or V+
INH
ISL43640
8
FN6043.3
January 23, 2006
Detailed Description
The ISL43640 operates from a single 2V to 12V supply with
low on-resistance (115) and high speed operation
(t
ON
= 60ns, t
OFF
= 30ns) with a +5V supply. The ISL43640
is especially well suited to portable battery powered
equipment thanks to the low operating supply voltage (2.0V),
low power consumption (3µW), low leakage currents (5nA
max), and the tiny
MSOP and QFN packaging. High frequency
applications also benefit from the wide bandwidth, and the
very high off isolation (75dB).
Supply Sequencing And Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and GND (see
Figure 7). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and input signal
voltages must remain between V+ and GND. If these
conditions cannot be guaranteed, then one of the following
two protection methods should be employed.
Logic inputs can easily be protected by adding a 1k
resistor in series with the input (see Figure 7). The resistor
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
This method is not applicable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low R
ON
switch, so two small signal
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (see Figure 7). These
additional diodes limit the analog signal from 1V below V+ to
1V above GND. The low leakage current performance is
unaffected by this approach, but the switch resistance may
increase, especially at low supply voltages.
Power-Supply Considerations
The ISL43640 construction is typical of most CMOS analog
switches, except that they have only two supply pins: V+ and
GND. V+ and GND drive the internal CMOS switches and
set their analog voltage limits. Unlike switches with a 13V
maximum supply voltage, the ISL43640’s 15V maximum
supply voltage provides plenty of room for the 10% tolerance
of 12V supplies, as well as room for overshoot and noise
spikes.
The minimum recommended supply voltage is 2.0V. It is
important to note that the input signal range, switching times,
and on-resistance degrade at lower supply voltages. Refer
to the electrical specification tables and Typical Performance
curves for details.
V+ and GND also power the internal logic and level shifters.
The level shifters convert the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.
The device cannot be operated with bipolar supplies,
because the input switching point becomes negative in this
configuration.
Logic-Level Thresholds
The ISL43640 is TTL compatible (0.8V and 2.4V) over a
supply range of 3V to 11V (see Figure 10). At 12V the V
IH
level is about 2.5V. This is still below the TTL guaranteed
high output minimum level of 2.8V, but noise margin is
reduced. For best results with a 12V supply, use a logic
family the provides a V
OH
greater than 3V.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails (see
Figure 11). Driving the digital input signals from GND to V+
with a fast transition time minimizes power dissipation.The
ISL43640 has been designed to minimize the supply current
whenever the digital input voltage is not driven to the supply
rails (0V to V+). For example driving the device with 3V logic
(0V to 3V) while operating with a 5V supply the device draws
only 10µA of current (see Figure 11 for
V
IN
= 3V). Similiar
devices of competitors can draw 8 times this amount of
current.
High-Frequency Performance
In 50 systems, signal response is reasonably flat even past
100MHz (see Figure 16). Figure 16 also illustrates that the
frequency response is very consistent over a wide V+ range,
and for varying analog signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal feed
through from a switch’s input to its output. Off Isolation is the
resistance to this feed through. Figure 17 details the high Off
Isolation rejection provided by this family. At 10MHz, Off
Isolation is about 55dB in 50 systems, decreasing
approximately 20dB per decade as frequency increases.
Higher load impedances decrease Off Isolation due to the
FIGURE 7. OVERVOLTAGE PROTECTION
GND
V
COM
V
NO or NC
OPTIONAL PROTECTION
V+
IN
DIODE
OPTIONAL PROTECTION
DIODE
OPTIONAL
PROTECTION
RESISTOR
FOR LOGIC
INPUTS
1k
ADD
X
1k
ISL43640
9
FN6043.3
January 23, 2006
voltage divider action of the switch OFF impedance and the
load impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND. One of
these diodes conducts if any analog signal exceeds V+ or
GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analog-
signal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and V+ or GND.
Typical Performance Curves T
A
= 25°C, Unless Otherwise Specified
FIGURE 8. ON RESISTANCE vs SUPPLY VOLTAGE FIGURE 9. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 10. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
FIGURE 11. SUPPLY CURRENT vs DIGITAL ADDRESS INPUT
VOLTAGE
25791112
0
100
200
300
400
500
R
ON
()
V+ (V)
V
COM
= (V+) - 1V
I
COM
= 1mA
-40°C
85°C
25°C
3 4 6 8 10 13
R
ON
()
V
COM
(V)
0 4 6 8 10 12
2
V+ = 3.3V
I
COM
= 1mA
30
40
50
60
70
80
85°C
-40°C
25°C
V+ = 12V
60
80
100
120
140
25°C
-40°C
85°C
V+ = 5V
75
100
150
200
225
175
125
25°C
-40°C
85°C
V+ (V)
25
3.0
2.5
2.0
1.5
1.0
0.5
34 678910111213
V
INH
AND
V
INL
(V)
3.0
2.5
2.0
1.5
1.0
0.5
-40°C
V
INL
85°C
-40°C
85°C
V
INH
25°C
25°C
01.50.51 22.533.544.55
70
60
50
40
30
20
10
0
V
IN(ADD)
(V)
I
CC
(µA)
V+ = +5V
ISL43640

ISL43640IU

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC MUX/DEMUX 4X1 10MSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union