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IDT71V432S10PF8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
6.42
13
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 — Byte Controlled
(1,2,3)
NOTES:
1. ZZ input is LOW, GW is HIGH, and LBO is Don’t Care for this cycle.
2. O4(Aw) represents the final output data in the burst sequence of the base address Aw. I1(Ax) represents the first input from the external address Ax. I1(Ay) represents the first input from the external address
Ay; I2(Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A
0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
In the case of input I2(Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS
0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
A
D
D
R
E
S
S
C
L
K
A
D
S
P
A
D
S
C
t
C
Y
C
t
S
S
t
H
S
t
C
H
t
C
L
t
H
A
t
S
A
A
x
A
y
B
W
x
A
D
V
D
A
T
A
O
U
T
O
E
t
H
C
t
S
D
S
i
n
g
l
e
W
r
i
t
e
B
u
r
s
t
W
r
i
t
e
I
1
(
A
x
)
I
2
(
A
y
)
I
2
(
A
y
)
(
A
D
V
s
u
s
p
e
n
d
s
b
u
r
s
t
)
I
2
(
A
z
)
t
H
D
B
u
r
s
t
R
e
a
d
E
x
t
e
n
d
e
d
B
u
r
s
t
W
r
i
t
e
t
O
H
Z
D
A
T
A
I
N
t
S
A
V
t
S
W
O
4
(
A
w
)
C
E
,
C
S
1
B
W
E
t
S
W
(
N
o
t
e
3
)
I
1
(
A
z
)
A
z
I
4
(
A
y
)
I
1
(
A
y
)
3
1
0
4
d
r
w
0
9
I
4
(
A
y
)
I
3
(
A
y
)
t
S
C
B
W
E
i
s
i
g
n
o
r
e
d
w
h
e
n
A
D
S
P
i
n
i
t
i
a
t
e
s
b
u
r
s
t
B
W
x
i
s
i
g
n
o
r
e
d
w
h
e
n
A
D
S
P
i
n
i
t
i
a
t
e
s
b
u
r
s
t
I
3
(
A
z
)
O
3
(
A
w
)
t
H
W
t
H
W
6.42
14
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Timing Waveform of Sleep (ZZ) and Power-Down Modes
(1,2,3)
NOTES:
1. Device must power up in deselected Mode.
2. LBO input is Don’t Care for this cycle.
3. It is not necessary to retain the state of the input registers throughout the Power-down cycle.
4. CS
0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
t
C
Y
C
t
S
S
t
C
L
t
C
H
t
H
A
t
S
A
t
S
C
t
H
C
t
O
E
t
O
L
Z
t
H
S
C
L
K
A
D
S
P
A
D
S
C
A
D
D
R
E
S
S
G
W
C
E
,
C
S
1
A
D
V
D
A
T
A
O
U
T
O
E
Z
Z
S
i
n
g
l
e
R
e
a
d
S
n
o
o
z
e
M
o
d
e
t
Z
Z
P
W
3
1
0
4
d
r
w
1
0
O
1
(
A
x
)
A
x
(
N
o
t
e
4
)
t
Z
Z
R
A
z
6.42
15
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
CLK
ADSP or ADSC
ADDRESS
DATA
OUT
Av Aw Ax Ay Az
(Av) (Aw) (Ax) (Ay)
3104 drw 11
Non-Burst Read Cycle Timing Waveform
(1,2,3,4)
NOTES:
1. ZZ, CE, CS1, and OE are LOW for this cycle.
2. ADV, GW, BWE, BWx, and CS0 are HIGH for this cycle.
3. (Ax) represents the data for address Ax, etc.
4. For read cycles, ADSP and ADSC function identically and are therefore interchangeable.
CLK
ADSP
GW or
BW E and BWx
ADDRESS
ADSC
DATA
IN
Av Aw Ax AzAy
(Av) (Aw) (Ax) (Az)(Ay)
3104 drw 12
Non-Burst Write Cycle Timing Waveform
(1,2,3,4)
NOTES:
1. ZZ, CE and CS1 are LOW for this cycle.
2. ADV, OE and CS0 are HIGH for this cycle.
3. (AX) represents the data for address AX, etc.
4. For write cycles, ADSP and ADSC have different limitations.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

IDT71V432S10PF8

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Buy IDT71V432S10PF8
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Description:
IC SRAM 1M PARALLEL 100TQFP
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New from this manufacturer.
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