6.42
12
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
A
D
D
R
E
S
S
C
L
K
A
D
S
P
A
D
S
C
t
C
Y
C
t
S
S
t
H
S
t
C
H
t
C
L
t
H
A
t
S
A
A
x
A
y
A
z
A
D
V
D
A
T
A
O
U
T
O
E
t
H
C
t
S
D
I
1
(
A
x
)
I
1
(
A
z
)
I
2
(
A
y
)
t
H
D
t
O
H
Z
D
A
T
A
I
N
t
H
A
V
O
3
(
A
w
)
O
4
(
A
w
)
C
E
,
C
S
1
G
W
t
S
W
(
N
o
t
e
3
)
I
2
(
A
z
)
B
u
r
s
t
W
r
i
t
e
B
u
r
s
t
R
e
a
d
3
1
0
4
d
r
w
0
8
B
u
r
s
t
W
r
i
t
e
S
i
n
g
l
e
W
r
i
t
e
I
3
(
A
z
)
I
4
(
A
y
)
I
3
(
A
y
)
I
2
(
A
y
)
t
S
A
V
(
A
D
V
s
u
s
p
e
n
d
s
b
u
r
s
t
)
I
1
(
A
y
)
B
W
E
i
s
i
g
n
o
r
e
d
w
h
e
n
A
D
S
P
i
n
i
t
i
a
t
e
s
b
u
r
s
t
t
S
C
.
t
H
W
Timing Waveform of Write Cycle No. 1 — GW Controlled
(1,2,3)
NOTES:
1. ZZ input is LOW, BWE is HIGH, and LBO is Don’t Care for this cycle.
2. O4(Aw) represents the final output data in the burst sequence of the base address Aw. I1(Ax) represents the first input from the external address Ax. I1(Ay) represents the first input from the external address
Ay; I2(Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
In the case of input I2(Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS
0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
