ADP1864 Data Sheet
Rev. C | Page 8 of 16
THEORY OF OPERATION
The ADP1864 is a constant frequency (580 kHz), current-mode
buck controller. PGATE drives the gate of the external P-channel
FET. The duty cycle of the external FET dictates the output
voltage and the current supplied to the load.
The peak inductor current is measured across the external sense
resistor, while the system output voltage is fed back through an
external resistor divider to the FB pin.
At the start of every oscillator cycle, PGATE turns on the
external FET, causing the inductor current, and therefore the
current sense amplifier voltage, to increase. The inductor
current increases until the current amplifier voltage equals
the voltage at the COMP pin. This resets the internal flip-flop,
causing PGATE to go high and turning off the external FET.
The inductor current decreases until the beginning of the next
oscillator period.
The voltage at the COMP node is the output of the internal
error amplifier. The negative input of the error amplifier is the
output voltage scaled by an external resistive divider, and the
positive input to the error amplifier is driven by a 0.8 V band
gap reference. An increase in the load current causes a small
drop in the feedback voltage, in turn causing an increase in the
COMP voltage and, therefore, the duty cycle. The resulting
increase in the on time of the FET provides the additional
current required by the load.
LOOP STARTUP
Pulling the COMP pin to GND disables the ADP1864. When
the COMP pin is released from GND, an internal 0.6 μA current
source charges the external compensation capacitor on the
COMP node. Once the COMP voltage has charged to 0.67 V,
the internal control blocks are enabled and COMP is pulled up
to its minimum normal operating voltage (0.9 V). As the voltage at
COMP continues to increase, the on time of the external FET
increases to supply the required inductor current. The loop
stabilizes completely once the COMP voltage is sufficiently high
to support the load current. The regulation voltage at FB is 0.8 V.
ICMP
R
S
Q
RSI
SLOPE
COMP
OSC
FREQUENCY
FOLDBACK
0.35V
V
IN
0.3V
GND
COMP
CSIN
SHORT-CIRCUIT
DETECT
15mV
UVLO,
SWITCHING
LOGIC AND
BLANKING
CIRCUIT
OVP
EAMP
UVLO
VREF
+
80mV
VREF
0.8V
2
5
4
V
IN
0.8V
3
6
FB
PGATE
VREF
VREF
0.8V
UVLO
SHDN
UV
SHDN
CMP
0.3V
V
IN
0.6µA
G
S
D
2.5V
2A
ADP1864
05562-013
V
IN
= 3.15V TO 14V
1
Figure 12. Functional Block Diagram
