REVISION A 10/26/15
844021-01 DATA SHEET
7 FEMTOCLOCKS™ CRYSTAL-TO-LVDS
CLOCK GENERATOR
APPLICATION INFORMATION
FIGURE 2. CRYSTAL INPUt INTERFACE
CRYSTAL INPUT INTERFACE
The 844021-01 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The optimum C1 and C2 values can be slightly adjusted for different
board layouts.
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 844021-01 provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. V
DD
and V
DDA
should be individually connected to
the power supply plane through vias, and 0.01µF bypass capacitors
should be used for each pin. Figure 1 illustrates this for a generic V
DD
pin and also shows that V
DDA
requires that an additional10Ω resistor
along with a 10µF bypass capacitor be connected to the V
DDA
pin.
FIGURE 1. POWER SUPPLY FILTERING
10Ω
V
DDA
10μF
.01μF
3.3V or 2.5V
.01μF
V
DD
