13
LTC34 48
3448f
APPLICATIO S I FOR ATIO
WUUU
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25 • C
LOAD
).
Thus, a 10µF capacitor charging to 3.3V would require a
250µs rise time, limiting the charging current to about
130mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3448. These items are also illustrated graphically in
Figures 7 and 8. Check the following in your layout:
1. The power traces, consisting of the GND trace, the SW
trace and the V
IN
trace should be kept short, direct and
wide.
2. Does the V
FB
pin connect directly to the feedback
resistors? The resistive divider R1/R2 must be con-
nected between the (+) plate of C
OUT
and ground.
3. Does the (+) plate of C
IN
connect to V
IN
as closely as
possible? This capacitor provides the AC current to the
internal power MOSFETs.
4. Keep the switching node, SW, away from the sensitive
V
FB
node.
5. Keep the (–) plates of C
IN
and C
OUT
as close as possible.
Design Example
As a design example, assume the LTC3448 is used in a
single lithium-ion battery-powered cellular phone
application. The V
IN
will be operating from a maximum of
4.2V down to about 2.7V. The load current requirement
is a maximum of 0.6A but most of the time it will be in
standby mode, requiring only 2mA. Efficiency at both low
Figure 7. LTC3448 Layout Design
Figure 8. LTC3448 Layout
V
IN
9
1
3
R
FB2
R
FB1
2
5
C
IN
V
IN
LTC3448
FREQ
SYNC
L
3448 F07
SW
4
8
6
7
RUN
V
OUT
MODE
V
FB
GND
C
OUT
C
FF
V
OUT
3448 F08
