10
LTC34 48
3448f
APPLICATIO S I FOR ATIO
WUUU
Inductor Core Selection
Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy mate-
rials are small and don’t radiate much energy, but gener-
ally cost more than powdered iron core inductors with
similar electrical characteristics. The choice of which style
inductor to use often depends more on the price vs size
requirements and any radiated field/EMI requirements
than on what the LTC3448 requires to operate. Table 1
shows some typical surface mount inductors that work
well in LTC3448 applications.
temperature than required. Always consult the manufac-
turer if there is any question.
The selection of C
OUT
is driven by the required effective
series resistance (ESR). Typically, once the ESR require-
ment for C
OUT
has been met, the RMS current rating
generally far exceeds the I
RIPPLE(P-P)
requirement. In any
case, if LDO mode is enabled, the value of C
OUT
must have
a minimum value of 2µF to ensure loop stability. The
output ripple V
OUT
is determined by:
∆≅ +
V I ESR
fC
OUT L
OUT
1
8
where f = operating frequency, C
OUT
= output capacitance
and I
L
= ripple current in the inductor. For a fixed output
voltage, the output ripple is highest at maximum input
voltage since I
L
increases with input voltage.
Aluminum electrolytic and dry tantalum capacitors are
both available in surface mount configurations. In the case
of tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. An excellent choice is
the AVX TPS series of surface mount tantalum. These are
specially constructed and tested for low ESR so they give
the lowest ESR for a given volume. Other capacitor types
include Sanyo POSCAP, Kemet T510 and T495 series, and
Sprague 593D and 595D series. Consult the manufacturer
for other specific recommendations.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. Because the
LTC3448’s control loop does not depend on the output
capacitor’s ESR for stable operation, ceramic capacitors
can be used freely to achieve very low output ripple and
small circuit size.
However, care must be taken when ceramic capacitors are
used at the input and the output. When a ceramic capacitor
is used at the input and the power is supplied by a wall
adapter through long wires, a load step at the output can
induce ringing at the input, V
IN
. At best, this ringing can
couple to the output and be mistaken as loop instability. At
Table 1. Representative Surface Mount Inductors
PART VALUE DCR MAX DC SIZE
NUMBER (µH) ( MAX) CURRENT (A) W × L × H (mm
3
)
Sumida 1.5 0.043 1.55 3.8 × 3.8 × 1.8
CDRH3D16 2.2 0.075 1.20
3.3 0.110 1.10
4.7 0.162 0.90
Sumida 2.2 0.116 0.950 3.5 × 4.3 × 0.8
CMD4D06 3.3 0.174 0.770
4.7 0.216 0.750
Coilcraft 2.2 0.104 1.8 2.5 × 3.2 × 2.0
ME3220 3.3 0.138 1.3
4.7 0.190 1.2
Murata 1.0 0.060 1.00 2.5 × 3.2 × 2.0
LQH3C 2.2 0.097 0.79
4.7 0.150 0.65
C
IN
and C
OUT
Selection
In continuous mode, the source current of the top MOS-
FET is a square wave of duty cycle V
OUT
/V
IN
. To prevent
large voltage transients, a low ESR input capacitor sized
for the maximum RMS current must be used. The maxi-
mum RMS capacitor current is given by:
CI
VVV
V
IN OMAX
OUT IN OUT
IN
required I
RMS
()
[]
12/
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT
/2. This simple worst-case condition is com-
monly used for design. Note that the capacitor
manufacturer’s ripple current ratings are often based on
2000 hours of life. This makes it advisable to further derate
the capacitor, or choose a capacitor rated at a higher
11
LTC34 48
3448f
worst, a sudden inrush of current through the long wires
can potentially cause a voltage spike at V
IN
, large enough
to damage the part.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
Output Voltage Programming
The output voltage is set by tying V
FB
to a resistive divider
according to the following formula:
VV
R
R
OUT
=+
06 1
2
1
.
(2)
The external resistive divider is connected to the output,
allowing remote voltage sensing as shown in Figure 5.
APPLICATIO S I FOR ATIO
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Figure 6. Power Loss vs Load Current
LOAD CURRENT (A)
0.0001
0.0001
POWER LOSS (W)
0.01
1
0.010.001 10.1
3448 F06
0.001
0.1
1.2V
1.5V
1.8V
V
IN
= 3.6V
FREQ = 0V
LDOCNTRL = V
OUT(AUTO)
loss dominates the efficiency loss at low load currents,
whereas the I
2
R loss dominates the efficiency loss at
medium to high load currents. At very low load currents
with the part operating in LDO mode, efficiency can be
dominated by I
2
R losses in the pass transistor and is a
strong function of (V
IN
– V
OUT
). In a typical efficiency plot,
the efficiency curve at very low load currents can be
misleading since the actual power lost is of little conse-
quence as illustrated in Figure 6.
Figure 5. Setting the LTC3448 Output Voltage
V
FB
GND
LTC3448
0.6V V
OUT
5.5V
R2
R1
3448 F05
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC3448 circuits: V
IN
quiescent current and I
2
R
losses. When in switching mode, V
IN
quiescent current
1. The V
IN
quiescent current is due to two components:
the DC bias current as given in the Electrical Character-
istics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge, dQ, moves from V
IN
to ground. The resulting
dQ/dt is the current out of V
IN
that is typically larger than
the DC bias current and proportional to frequency. Both
the DC bias and gate charge losses are proportional to
V
IN
and thus their effects will be more pronounced at
higher supply voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor R
L
. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
12
LTC34 48
3448f
APPLICATIO S I FOR ATIO
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top and bottom MOSFET R
DS(ON)
and the duty cycle
(DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteris-
tics curves. Thus, to obtain I
2
R losses, simply add R
SW
to R
L
and multiply the result by the square of the
average output current.
3. At load currents below the selected threshold the
LTC3448 will switch into low ripple LDO mode if en-
abled. In this case the losses are due to the DC bias
currents as given in the electrical characteristics and
I
2
R losses due to the (V
IN
– V
OUT
) voltage drop across
the internal pass transistor.
Other losses when in switching operation, including C
IN
and COUT ESR dissipative losses and inductor core losses,
generally account for less than 2% total additional loss.
Thermal Considerations
The LTC3448 requires the package backplane metal (GND
pin) to be well soldered to the PC board. This gives the DFN
and MSOP packages exceptional thermal properties, mak-
ing it difficult in normal operation to exceed the maximum
junction temperature of the part. In most applications the
LTC3448 does not dissipate much heat due to its high
efficiency. In applications where the LTC3448 is running at
high ambient temperature with low supply voltage and high
duty cycles, such as in dropout, the heat dissipated may
exceed the maximum junction temperature of the part if it
is not well thermally grounded. If the junction temperature
reaches approximately 150°C, both power switches will be
turned off and the SW node will become high impedance.
To avoid the LTC3448 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
T
R
= P
D
θ
JA
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to the
ambient temperature.
The junction temperature, T
J
, is given by:
T
J
= T
A
+ T
R
where T
A
is the ambient temperature.
As an example, consider the LTC3448 in dropout at an
input voltage of 2.7V, a load current of 600mA and an
ambient temperature of 70°C. From the typical perfor-
mance graph of switch resistance, the R
DS(ON)
of the
P-channel switch at 70°C is approximately 0.52. There-
fore, power dissipated by the part is:
P
D
= I
LOAD
2
• R
DS(ON)
= 187.2mW
For the 3mm × 3mm DFN package, the θ
JA
is 43°C/W.
Thus, the junction temperature of the regulator is:
T
J
= 85°C + (0.1872)(43) = 93°C
which is well below the maximum junction temperature of
125°C.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance R
DS(ON).
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to (I
LOAD
• ESR), where ESR is the effective series
resistance of C
OUT
. I
LOAD
also begins to charge or dis-
charge C
OUT
, which generates a feedback error signal. The
regulator loop then acts to return V
OUT
to its steady-state
value. During this recovery time V
OUT
can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. For a detailed explanation of switching control loop
theory, see Application Note 76.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel

LTC3448EDD#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 600mA, Synch Step-Down Reg in DFN
Lifecycle:
New from this manufacturer.
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