AR0238
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14
ANALOG/DIGITAL GAINS
A programmable analog gain of 1.0x to 16x (linear and
HDR) applied simultaneously to all color channels will be
featured along with a digital gain of 1x to 16x that may be
configured on a per color channel basis. Analog gain can be
applied per exposure in line interleaved mode.
SKIPPING/BINNING MODES
The AR0238 supports subsampling. Subsampling allows
the sensor to read out a smaller set of active pixels by either
skipping, binning, or summing pixels within the readout
window. Horizontal binning is achieved in the digital
readout. The sensor will sample the combined 2x adjacent
pixels within the same color plane. Vertical row binning is
applied in the pixel readout. Row binning can be configured
as 2x rows within the same color plane. Pixel skipping can
be configured up to 2x in both the x−direction and
y−direction. Skipping pixels in the x−direction will not
reduce the row time. Skipping pixels in the y direction will
reduce the number of rows from the sensor effectively
reducing the frame time. Skipping will introduce image
artifacts from aliasing.
The AR0238 supports row wise vertical binning. Row
wise vertical summing is only supported in monochrome
sensors.
CLOCKING OPTIONS
The sensor contains a phase−locked loop (PLL) that is
used for timing generation and control. The required VCO
clock frequency is attained through the use of a pre−PLL
clock divider followed by a multiplier. The PLL multiplier
should be an even integer. If an odd integer (M) is
programmed, the PLL will default to the lower (M−1) value
to maintain an even multiplier value. The multiplier is
followed by a set of dividers used to generate the output
clocks required for the sensor array, the pixel analog and
digital readout paths, and the output parallel and serial
interfaces. Use of the PLL is required when using the HiSPi
interface.
TEMPERATURE SENSOR
The AR0238 sensor has a built-in PTAT-based
temperature sensor, accessible through registers, that is
capable of measuring die junction temperature. The value
read out from the temperature sensor register is an ADC
output value that needs to be converted downstream to a
final temperature value in degrees Celsius. Since the PTAT
device characteristic response is quite linear in the
temperature range of operation required, a simple linear
function can be used to convert the ADC output value to the
final temperature in degrees Celsius.
A single reference point will be made available via
register read as well as a slope for back−calculating the
junction temperature value. An error of +/-5% or better over
the full specified operating range of the sensor is to be
expected.
SILICON / FIRMWARE / SEQUENCER REVISION
INFORMATION
A revision register will be provided to read out (via I
2
C)
silicon and sequencer/OTPM revision information. This
will be helpful to distinguish among different lots of material
if there are future OTPM or sequencer revisions.
LENS SHADING CORRECTION
The latest lens shading correction algorithm will be
included for potential low Z height applications.
COMPRESSION
When the AR0238 is configured for linear mode
operation, the sensor can optionally compress 12−bit data to
10−bit using A−law compression. The A−law compression
is disabled by default.
PACKAGING
The AR0238 will be offered in a 11.43 x 11.43 48−Lead
mPLCC package.
PARALLEL INTERFACE
The parallel pixel data interface uses these output−only
signals:
• FRAME_VALID
• LINE_VALID
• PIXCLK
• DOUT[11:0]
HIGH SPEED SERIAL PIXEL (HISPI) INTERFACE
The HiSPi interface supports three protocols,
Streaming−S, Streaming−SP, and Packetized SP. The
streaming protocols conform to a standard video application
where each line of active or intra−frame blanking provided
by the sensor is transmitted at the same length. The
Packetized SP protocol will transmit only the active data
ignoring line−to−line and frame−to−frame blanking data.
The HiSPi interface building block is a unidirectional
differential serial interface with four data and one double
data rate (DDR) clock lanes. One clock for every four serial
data lanes is provided for phase alignment across multiple
lanes. The AR0238 supports serial data widths of 10 or 12
bits on one, two, or four lanes. The specification includes a
DLL to compensate for differences in group delay for each
data lane. The DLL is connected to the clock lane and each
data lane, which acts as a control master for the output delay
buffers. Once the DLL has gained phase lock, each lane can
be delayed in
1/8 unit interval (UI) steps. This additional delay allows
the user to increase the setup or hold time at the receiver
circuits and can be used to compensate for skew introduced
in PCB design. Delay compensation may be set for clock
and/or data lines in the hispi_timing register R0x31C0. If the
DLL timing adjustment is not required, the data and clock
lane delay settings should be set to a default code of 0x0000
to reduce jitter, skew, and power dissipation.
