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PRELIMINARY DATA
March 2004
STP80NF55L-08
STB80NF55L-08 - STB80NF55L-08-1
N-CHANNEL 55V - 0.0065Ω - 80A - TO-220/D
2
PAK/I
2
PAK
STripFET™ II POWER MOSFET
(1) Current Limited by Package
(2) I
SD
≤ 80A, di/dt ≤ 500A/µs, V
DD
=40VT
j
≤ T
JMAX.
(3) Starting T
j
=25°C,I
D
=40A,V
DD
=40V
■ TYPICAL R
DS
(on) = 0.0065Ω
■ LOW THRESHOLD DRIVE
■ LOGIC LEVEL DEVICE
DESCRIPTION
This Power Mosfet is the latest development of
STMicroelectronics unique “Single Feature
Size
™” strip-based process. The resulting tran-
sistor shows extremely high packing density for
low on-resistance, rugged avalance characteris-
tics and less critical alignment steps therefore a re-
markable manufacturing reproducibility.
APPLICATIONS
■ HIGH CURRENT SWITCHING APPLICATION
ABSOLUTE MAXIMUM RATINGS
( ) Pulse width limited by safe operating area
TYPE V
DSS
R
DS(on)
I
D
STP80NF55L-08
STB80NF55L-08
STB80NF55L-08-1
55 V
55 V
55 V
0.008Ω
0.008Ω
0.008Ω
80 A
80 A
80 A
Symbol Parameter Value Unit
V
DS
Drain-source Voltage (V
GS
=0)
55 V
V
DGR
Drain-gate Voltage (R
GS
=20kΩ)
55 V
V
GS
Gate- source Voltage ± 16 V
I
D
(1) Drain Current (continuous) at T
C
= 25°C
80 A
I
D
(1) Drain Current (continuous) at T
C
= 100°C
80 A
I
DM
( )
Drain Current (pulsed) 320 A
P
TOT
Total Dissipation at T
C
= 25°C
300 W
Derating Factor 2 W/°C
dv/dt (2) Peak Diode Recovery voltage slope 15 V/ns
E
AS
(3)
Single Pulse Avalanche Energy 870 mJ
T
stg
Storage Temperature –55 to 175 °C
T
j
Max. Operating Junction Temperature 175 °C
TO-220
1
2
3
1
3
D
2
PAK
1
2
3
I
2
PAK
INTERNAL SCHEMATIC DIAGRAM
