Pin connection L6393
4/19 DocID14497 Rev 5
2 Pin connection
Figure 2. Pin connection (top view)
Table 1. Pin description
Pin no. Pin name Type Function
1 PHASE I Driver logic input (active high)
2 SD
(1)
1. The circuit provides less than 1 V on the LVG and HVG pins (at I
sink
= 10 mA), with V
CC
> 3 V. This allows
omitting the “bleeder” resistor connected between the gate and the source of the external MOSFET
normally used to hold the pin low; the gate driver assures low impedance also in SD
condition.
I Shutdown input (active low)
3 BRAKE
I Driver logic input (active low)
4 VCC P Lower section supply voltage
5 DT I Deadtime setting
6 CPOUT O Comparator output (open drain)
7 GND P Ground
8 CP- I Comparator negative input
9 CP+ I Comparator positive input
10 LVG
(1)
O Low-side driver output
11 NC Not connected
12 OUT P High-side (floating) common voltage
13 HVG
(1)
O High-side driver output
14 BOOT P Bootstrapped supply voltage
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DocID14497 Rev 5 5/19
L6393 Truth table
19
3 Truth table
In the L6393 IC the two input signals PHASE and BRAKE are fed into an AND logic port and
the resulting signal is in phase with the high-side output HVG and in opposition of phase
with the low-side output LVG. This means that if BRAKE
is kept to a high level, the PHASE
signal drives the half bridge in phase with the HVG output and in opposition of phase with
the LVG output. If BRAKE
is set to a low level, the low-side output LVG is always ON and
the high-side output HVG is always OFF, whatever the PHASE signal. This kind of logic
interface provides the possibility to control the power stages using the PHASE signal to
select the current direction in the bridge and the BRAKE
signal to perform current slow
decay on the low-sides.
From the point of view of the logic operations the two signals PHASE and BRAKE
are
completely equivalent, that means the two signals can be exchanged without any change in
the behavior on the resulting output signals (see Figure 1).
Note: The deadtime between the turn-OFF of one power switch and the turn-ON of the other
power switch is defined by the resistor connected between the DT pin and the ground.
Table 2. Truth table
Inputs Outputs
SD
PHASE BRAKE LVG HVG
L X
(1)
1. X: don’t care.
X
(1)
L L
H L L H L
H L H H L
H H L H L
H H H L H
Electrical data L6393
6/19 DocID14497 Rev 5
4 Electrical data
4.1 Absolute maximum ratings
4.2 Thermal data
Table 3. Absolute maximum ratings
Symbol Parameter
Value
Unit
Min. Max.
V
CC
Supply voltage -0.3 21 V
V
OUT
Output voltage V
BOOT
- 21 V
BOOT
+ 0.3 V
V
BOOT
Bootstrap voltage -0.3 620 V
V
hvg
High-side gate output voltage V
OUT
- 0.3 V
BOOT
+ 0.3 V
V
lvg
Low-side gate output voltage -0.3 V
CC
+ 0.3 V
V
CP+
Comparator positive input voltage -0.3 V
CC
+ 0.3 V
V
CP-
Comparator negative input voltage -0.3 V
CC
+ 0.3 V
V
i
Logic input voltage -0.3 15 V
V
od
Open drain voltage -0.3 15 V
dV
OUT
/dt Allowed output slew rate 50 V/ns
P
tot
Total power dissipation (T
A
= 25 °C) 800 mW
T
J
Junction temperature 150 °C
T
STG
Storage temperature -50 150 °C
ESD Human body model 2 kV
Table 4. Thermal data
Symbol Parameter SO-14 Unit
R
th(JA)
Thermal resistance junction to ambient max. 120 °C/W

L6393DTR

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Gate Drivers HALF-BRIDGE GATE DRIVER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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