MAX13013/MAX13014/MAX3023
+1.2V to +3.6V, 0.1µA, 100Mbps,
Single-/Dual-/Quad-Level Translators
_______________________________________________________________________________________ 7
Pin Description—MAX13013/MAX13014/
MAX3023 (Bidirectional Devices)
PIN
MAX3023 MAX13013 MAX13014
TSSOP
4 x 3
UCSP
SC70
3 x 2
UCSP
SOT23
3 x 3
UCSP
NAME FUNCTION
1 A1 4 B2 7 A2 I/O V
L
1 Input/Output 1, Referenced to V
L
2 B2 6 A3 I/O V
L
2 Input/Output 2, Referenced to V
L
3 A2 5 B1 8 A1 V
L
V
L
Input Voltage, +1.2V V
L
V
CC
- 0.4V
.
Bypass V
L
to GND
with a 0.1µF capacitor.
4 N.C. No Connection
5 B3 I/O V
L
3 Input/Output 3, Referenced to V
L
6 A3 I/O V
L
4 Input/Output 4, Referenced to V
L
7 A4 6 B3 5 B1 EN
Active-High Enable Input. If EN is pulled low, all inputs/outputs
are in tristate. Drive EN high (V
L
) for normal operation.
8 EN
Active-Low Enable Input. If EN is pulled high (V
L
), all inputs/
outputs are in tri-state. Drive EN low for normal operation
(MAX3023 TSSOP package only).
9 B4 I/O V
CC
4 Input/Output 4, Referenced to V
CC
10 C4 I/O V
CC
3 Input/Output 3, Referenced to V
CC
11 C3 2 A3 4 B3 GND Ground
12 C2 1 A1 1 C1 V
CC
V
CC
Input Voltage, +1.65V V
CC
+3.6V. Bypass V
CC
to GND
with a 0.1µF capacitor.
13 C1 3 C3 I/O V
CC
2 Input/Output 2, Referenced to V
CC
14 B1 3 A2 2 C2 I/O V
CC
1 Input/Output 1, Referenced to V
CC
MAX13013/MAX13014/MAX3023
+1.2V to +3.6V, 0.1µA, 100Mbps,
Single-/Dual-/Quad-Level Translators
8 _______________________________________________________________________________________
Test Circuits/Timing Diagrams
MAX13013
90%
50%
10%
I/O V
CC_
I/O V
L_
t
RISE/FALL
3ns
I/O
VL-VCC
C
IOVCC
EN
I/O V
L_
SOURCE
V
L
V
CC
I/O V
CC_
I/O
VL-VCC
t
RVCC
t
FVCC
90%
50%
10%
MAX13013
90%
50%
10%
SOURCE
I/O V
CC_
I/O V
CC_
I/O V
L_
t
RISE/FALL
3ns
I/O
VCC-VL
EN
V
L
V
CC
I/O
VCC-VL
t
RVL
t
FVL
90%
50%
10%
C
IOVL_
I/O V
L_
Figure 1. Driving I/O V
L_
Test Circuit and Timing
Figure 2. Driving I/O V
CC_
Test Circuit and Timing
MAX13013/MAX13014/MAX3023
+1.2V to +3.6V, 0.1µA, 100Mbps,
Single-/Dual-/Quad-Level Translators
_______________________________________________________________________________________ 9
Test Circuits/Timing Diagrams (continued)
MAX13013
SOURCE
I/O V
CC_
C
IOVCC
1M
EN
V
L
0
V
L
V
CC
0
0
I/O V
L_
I/O V
CC_
V
CC
/ 2
EN
V
L
I/O V
L_
MAX13013
SOURCE
C
IOVCC
I/O V
CC_
EN
I/O V
L_
1M
V
CC
t'
EN-VCC
EN
V
L
0
V
L
V
CC
0
0
I/O V
L_
t
EN-VCC
IS WHICH EVER IS LARGER BETWEEN t'
EN-VCC
AND t"
EN-VCC
.
I/O V
CC_
V
CC
/ 2
t"
EN-VCC
MAX13013
SOURCE
V
CC
EN
V
L
0
V
CC
V
L
0
0
I/O V
CC_
I/O V
L_
V
L
/ 2
EN
I/O V
L_
I/O V
CC_
MAX13013
SOURCE
EN
t'
EN-VL
EN
V
L
0
V
CC
V
L
0
0
I/O V
CC_
t
EN-VCC
IS WHICH EVER IS LARGER BETWEEN t'
EN-VCC
AND t"
EN-VCC
.
I/O V
L_
V
L
/ 2
t"
EN-VL
C
IOVL
100k
100k
C
IOVL
I/O V
L_
I/O V
CC_
V
L
Figure 3. Propagation Delay from I/O V
L_
to I/O V
CC_
After EN
Figure 4. Propagation Delay from I/O V
CC_
to I/O V
L_
After EN

MAX13014EKA+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Translation - Voltage Levels Dual 100Mbps
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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