JTAG-HS2™ Programming Cable for Xilinx FPGAs
Copyright Digilent, Inc. All rights reserved.
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3 Design Notes
The JTAG-HS2 uses high speed three-state buffers to drive the TMS, TDI, and TCK signals. These buffers are capable
of sourcing or sinking a maximum of 50 mA of current. The HS2 has 100 ohm resistors between the output of the
buffers and the I/O pins to ensure the cable does not exceed the maximum limit. To further limit short circuit
current, additional resistance may be placed in series with the I/O pins of the HS2 and the target board. However,
Digilent recommends limiting the amount of additional resistance to 100 ohms or less as higher resistance may
result in degraded operation.
When the JTAG-HS2 first receives power, the three-state buffers attached to the TMS, TDI, and TCK signals move
into a high-impedance state. They remain in the high-impedance state until an application enables the HS2's JTAG
or SPI port. Once these ports activate, the buffers actively drive the TMS, TDI, and TCK signals until the port is
disabled.
The IEEE 1149.7-2009 specification requires any device that functions as a debug and test system (DTS) to provide
a pull-up bias on the TMS and TDO pins. In order to meet this requirement, the JTAG-HS2 features weak pull-ups
(100K ohm) on the TMS, TDI, TDO, and TCK signals. While not strictly required, the pull-ups on the TDI and TCK
signals ensure that neither signal floats while another source is not actively driving them.
The JTAG-HS2 can interface scan chains that consist of one or more IEEE 1149-7 compatible Target Systems (TS).
The devices in these chains communicate using the TMS, TDI, TDO, and TCK signals or they may communicate
using only the TMS and TCK signals. Communication using only the TMS and TCK signals requires both the HS2 and
TS to drive the TMS pin. The current scan format, bit period, and the level of the TCK pin determine which device is
allowed to drive the TMS pin.
A drive conflict may occur when the HS2 and TS disagree on the current scan format setting or bit period. In the
event that a drive conflict occurs, the 100 ohm resistor between the TMS buffer and output pin will limit the
maximum current to 50 mA to prevent any damage from occurring to the JTAG-HS2. The drive conflict may be
resolved by having the JTAG-HS2 perform a reset escape, which will reset the scan format of the TS to
JScan0/JScan1. If the TMS pin of the TS is not capable of sourcing or sinking VDD (VREF) ÷ 100 amps of current then
an additional resistor should be placed in series with the TMS pin of the TS to further limit current flow.
In most cases a drive conflict can be avoided by having applications that use the HS2 communicate with the TS in
two-wire mode. Use the applications to reconfigure the TS to use the JScan0, JScan1, JScan2, or JScan3 scan
format prior to disabling the HS2's JTAG port.
The Adept SKD provides an example application that demonstrates how to communicate with a class T4 TAP
controller using the MScan, OScan0, and OScan1 scan formats.
