9397 750 14707 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 03 — 18 April 2005 5 of 14
Philips Semiconductors
PHB/PHD/PHU108NQ03LT
N-channel TrenchMOS™ logic level FET
6. Characteristics
Table 5: Characteristics
T
j
=25
°
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Static characteristics
V
(BR)DSS
drain-source breakdown voltage I
D
= 250 µA; V
GS
=0V
T
j
=25°C 25--V
T
j
= −55 °C 22--V
V
GS(th)
gate-source threshold voltage I
D
= 1 mA; V
DS
=V
GS
; Figure 9 and 10
T
j
=25°C 1 1.5 2 V
T
j
= 175 °C 0.5 - - V
T
j
= −55 °C - - 2.2 V
I
DSS
drain-source leakage current V
DS
=25V; V
GS
=0V
T
j
=25°C --1µA
T
j
= 175 °C - - 500 µA
R
G
gate resistance f = 1 MHz - 1.2 - Ω
I
GSS
gate-source leakage current V
GS
= ±10 V; V
DS
= 0 V - 0.02 100 nA
R
DSon
drain-source on-state resistance V
GS
=5V; I
D
=25A;Figure 6 and 8
T
j
=25°C - 6.7 7.5 mΩ
T
j
= 175 °C - 12.1 13.5 mΩ
V
GS
= 10 V; I
D
=25A;Figure 6 and 8 - 5.3 6 mΩ
Dynamic characteristics
Q
g(tot)
total gate charge I
D
= 25 A; V
DS
=12V; V
GS
= 4.5 V;
Figure 11 and 12
- 16.3 - nC
Q
gs
gate-source charge - 4 - nC
Q
gs1
pre-V
GS(th)
gate-source charge - 2.5 - nC
Q
gs2
post-V
GS(th)
gate-source charge - 1.5 - nC
Q
gd
gate-drain (Miller) charge - 5.6 - nC
V
plat
plateau voltage - 2.4 - V
Q
g(tot)
total gate charge I
D
= 0 A; V
DS
=0V; V
GS
= 4.5 V - 12.5 - nC
C
iss
input capacitance V
GS
=0V; V
DS
= 12 V; f = 1 MHz;
Figure 14
-1375-pF
C
oss
output capacitance - 640 - pF
C
rss
reverse transfer capacitance - 250 - pF
C
iss
input capacitance V
GS
=0V; V
DS
= 0 V; f = 1 MHz - 2120 - pF
t
d(on)
turn-on delay time V
DS
=12V; R
L
= 0.5 Ω; V
GS
= 4.5 V;
R
G
= 5.6 Ω
-15-ns
t
r
rise time -38-ns
t
d(off)
turn-off delay time - 32 - ns
t
f
fall time -25-ns
Source-drain diode
V
SD
source-drain (diode forward) voltage I
S
= 25 A; V
GS
=0V;Figure 13 - 0.86 1.2 V
t
rr
reverse recovery time I
S
= 20 A; dI
S
/dt = −100 A/µs; V
GS
=0V;
V
R
=25V
-34-ns
Q
r
recovered charge - 21 - nC
