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AD679AJ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
(T
MIN
to T
MAX
, V
CC
= +12 V 5%, V
EE
= –12 V 5%, V
DD
= +5 V 10%, unless otherwise noted)
AD679
REV. D
–3–
DC SPECIFICATIONS
AD679J/A/S AD679K/B/T
Parameter Min Typ Max Min Typ Max Unit
TEMPERATURE RANGE
J, K Grades 0 70 0 70 °C
A, B Grades –40 +85 –40 +85 °C
S, T Grades –55 +125 –55 +125 °C
ACCURACY
Resolution 14 14 Bits
Integral Nonlinearity (INL) 2 1 2.5 LSB
Differential Nonlinearity (DNL) 14 14 Bits
Unipolar Zero Error
1
(@ 25°C) 0.08 0.05 0.07 % FSR
2
Bipolar Zero Error
1
(@ 25°C) 0.08 0.05 0.07 % FSR
Gain Error
1, 3
(@ 25°C) 0.12 0.09 0.11 % FSR
Temperature Drift
Unipolar Zero
4
J, K Grades 0.04 0.04 0.05 % FSR
A, B Grades 0.05 0.05 0.07 % FSR
S, T Grades 0.09 0.09 0.10 % FSR
Bipolar Zero
4
J, K Grades 0.02 0.02 0.04 % FSR
A, B Grades 0.04 0.04 0.05 % FSR
S, T Grades 0.08 0.08 0.09 % FSR
Gain
4
J, K Grades 0.09 0.09 0.11 % FSR
A, B Grades 0.10 0.10 0.16 % FSR
S, T Grades 0.20 0.20 0.25 % FSR
Gain
5
J, K Grades 0.04 0.04 0.05 % FSR
A, B Grades 0.05 0.05 0.07 % FSR
S, T Grades 0.09 0.09 0.10 % FSR
ANALOG INPUT
Input Ranges
Unipolar Mode 0 +10 0 +10 V
Bipolar Mode –5 +5 –5 +5 V
Input Resistance 10 10 MΩ
Input Capacitance 10 10 pF
Input Settling Time 1.5 1.5 µs
Aperture Delay 10 10 ns
Aperture Jitter 150 150 ps
INTERNAL VOLTAGE REFERENCE
Output Voltage
6
4.98 5.02 4.98 5.02 V
External Load
Unipolar Mode 1.5 1.5 mA
Bipolar Mode 0.5 0.5 mA
POWER SUPPLIES
Power Supply Rejection
V
CC
= +12 V ± 5% 6 6 LSB
V
EE
= –12 V ± 5% 6 6 LSB
V
DD
= +5 V ± 10% 6 6 LSB
Operating Current
I
CC
18 20 18 20 mA
I
EE
25 34 25 34 mA
I
DD
8 12 8 12 mA
Power Consumption 560 745 560 745 m
W
NOTES
1
Adjustable to zero. See Figures 5 and 6.
2
% FSR = percent of full-scale range.
3
Includes internal voltage reference error.
4
Includes internal voltage reference drift.
5
Excludes internal voltage reference drift.
6
With maximum external load applied.
Specifications shown in boldface are tested on all devices at final electrical test with worst case supply voltages at T
MIN
, 25°C and T
MAX
. Results from those tests are used to
calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested.
Specifications subject to change without notice.
AD679
REV. D
–4–
Parameter Symbol Min Max Unit
SC Delay t
SC
50 ns
Conversion Time t
C
6.3 µs
Conversion Rate
1
t
CR
7.8 µs
Convert Pulse Width t
CP
0.097 3.0 µs
Aperture Delay t
AD
520ns
Status Delay t
SD
0 400 ns
Access Time
2, 3
t
BA
10 100 ns
10 57
4
ns
Float Delay
5
t
FD
10 80 ns
Output Delay t
OD
0ns
Format Setup t
FS
100 ns
OE Delay t
OE
20 ns
Read Pulse Width t
RP
195 ns
Conversion Delay t
CD
400 ns
EOCEN Delay t
EO
50 ns
NOTES
1
Includes acquisition time.
2
Measured from the falling edge of OE/EOCEN (0.8 V) to the time at which the
data lines/EOC cross 2.0 V or 0.8 V. See Figure 4.
3
C
OUT
= 100 pF.
4
C
OUT
= 50 pF.
5
Measured from the rising edge of OE/EOCEN (2.0 V) to the time at which the output voltage changes by 0.5. See Figure 4; C
OUT
= 10 pF.
Specifications subject to change without notice.
(All device types T
MIN
to T
MAX
, V
CC
= +12 V 5%, V
EE
= –12 V
5%, V
DD
= +5 V 10%)
NOTES
1
IN ASYNCHRONOUS MODE, STATE OF CS DOES NOT AFFECT OPERATION.
SEE THE START CONVERSION TRUTH TABLE FOR DETAILS.
2
EOCEN = LOW (SEE FIGURE 3). IN SYNCHRONOUS MODE, EOC IS A THREE-
STATE OUTPUT. IN ASYNCHRONOUS MODE, EOC IS AN OPEN DRAIN OUTPUT.
3
DATA SHOULD NOT BE ENABLED DURING A CONVERSION.
Figure 1. Conversion Timing
Figure 2. Output Timing
NOTE
1
EOC IS A THREE-STATE OUTPUT IN SYNCHRONOUS MODE
AND AN OPEN DRAIN OUTPUT IN ASYNCHRONOUS. ACCESS (t
BA
)
AND FLOAT (t
FD
) TIMING SPECIFICATIONS DO NOT APPLY IN
ASYNCHRONOUS MODE WHERE THEY ARE A FUNCTION OF THE
TIME CONSTANT FORMED BY THE 10pF OUTPUT CAPACITANCE
AND THE PULL-UP RESISTOR.
Figure 3. EOC Timing
TEST V
CP
C
OUT
ACCESS TIME HIGH Z TO LOGIC LOW 5V 100pF
FLOAT TIME LOGIC HIGH TO HIGH Z 0V 10pF
ACCESS TIME HIGH Z TO LOGIC HIGH 0V 100pF
FLOAT TIME LOGIC LOW TO HIGH Z 5V 10pF
I
OL
I
OH
D
OUT
V
CP
C
OUT
Figure 4. Load Circuit for Bus Timing Specifications
TIMING SPECIFICATIONS
AD679
REV. D
–5–
ABSOLUTE MAXIMUM RATINGS
1
With
Respect
Specification To Min Max Unit
V
CC
AGND –0.3 +18 V
V
EE
AGND –18 +0.3 V
V
CC
2
V
EE
–0.3 +26.4 V
V
DD
DGND 0 +7 V
AGND DGND –1 +1 V
AIN, REF
IN
AGND V
EE
V
CC
V
Digital Inputs DGND –0.5 +7 V
Digital Outputs DGND –0.5 V
DD
+ 0.3 V
Max Junction
Temperature 175 °C
With
Respect
Specification To Min Max Unit
Operating
Temperature
J and K Grades 0 70 °C
A and B Grades –40 +85 °C
S and T Grades –55 +125 °C
Storage Temperature –65 +150 °C
Lead Temperature
(10 sec max) 300 °C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
The AD679 is not designed to operate from ⫾15 V supplies.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD679 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ORDERING GUIDE
1
Temperature Tested and Package
Model Package Range Specified Option
2
AD679JN 28-Pin Plastic DIP 0°C to +70°CAC N-28
AD679KN 28-Pin Plastic DIP 0°C to +70°C AC + DC N-28
AD679JD 28-Pin Ceramic DIP 0°C to +70°CAC D-28
AD679KD 28-Pin Ceramic DIP 0°C to +70°C AC + DC D-28
AD679AD 28-Pin Ceramic DIP –40°C to +85°CAC D-28
AD679BD 28-Pin Ceramic DIP –40°C to +85°C AC + DC D-28
AD679SD 28-Pin Ceramic DIP –55°C to +125°CAC D-28
AD679TD 28-Pin Ceramic DIP –55°C to +125°C AC + DC D-28
AD679AJ 44-Lead Ceramic JLCC –40°C to +85°CAC J-44
AD679BJ 44-Lead Ceramic JLCC –40°C to +85°C AC + DC J-44
AD679SD/883B
3
NOTES
1
For parallel read (14-bits) interface to 16-bit buses, see AD779.
2
N = Plastic DIP; D = Ceramic DIP; J = J-Leaded Ceramic Chip Carrier.
3
For details, grade, and package offerings screened in accordance with MIL-STD-883, refer to the
Analog Devices Military Products Databook or the current AD679/883B data sheet.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

AD679AJ

Mfr. #:
Buy AD679AJ
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC IC 14-BIT 128 kSPS Complete SAMPLING
Lifecycle:
New from this manufacturer.
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